Best of Tessent at ITC 2022

Discover and access a wide range of ITC presentations from Siemens experts, customers and partners.

Along with its associated workshops and tutorials, ITC remains the best place to discover new technologies for DFT, IC test, yield learning and in-life monitoring and analytics.

Diamond Supporter Presentations

Siemens is proud to be a Diamond Supporter of the International Test Conference 2022. You can watch the recordings of the key Diamond Presentations below.

DFT to In-Life monitoring for electronic systems

Ankur Gupta, Vice President and GM, Tessent, Siemens EDA, introduces DFT to In-Life monitoring for electronic systems at ITC 2022.

Reducing design effort, test time & power with SSN

Dan Trock, Principal Engineer at Amazon Web Services, presents on reducing design effort, test time & power with SSN in AWS Custom Silicon.

Structural deterministic test in silicon lifecycle

Janusz Rajski, Vice President of Research and Development, Tessent, Siemens EDA, presents on structural deterministic test in the silicon lifecycle.

Advancements in DFT automation for 2.5D / 3D IC era

Vidya Neerkundar, Product Manager, Tessent, Siemens EDA introduces Advancements in DFT automation for 2.5D / 3D IC era.

Partner Presentations

Watching presentations in the Tessent theater is a tradition on the ITC exhibit floor, where our partners present their experiences with Tessent technologies, reference flows and collaboration projects. View a range of partner presentations below.

Renesas’ shift left with Design-for-Test using Tessent

Hiroyuki Iwata, Digital Design Technology at Renesas Electronics Corp. presents Renesas’ shift left with Design-for-Test using Tessent.

Analog defect coverage improvement using DefectSim

Analog defect coverage improvement using Tessent DefectSim presented by Neerja Bawaskar, Principle DFT Engineer, Post-Fab Test Development Center, GlobalFoundries.

Breakthrough yield barriers - Siemens & PDF Solutions

Breakthrough yield barriers with Siemens & PDF Solutions introduced by Siemens & Thomas Zanon, Engagement Director, PDF Solutions.

Implementing Scan Test with SSN

Phil Brock, Consulting Manager, Advantest, presents implementing scan test with SSN on-chip compare & diagnostic data collection on Advantest 93000.

The 1st ISO 26262 certified ASIL-B AI chip in China

Learn about the 1st ISO 26262 certified ASIL-B AI chip in China in this presentation by Victor Wang, DFT Engineer, Horizon Robotics.

Teradyne enabling Siemens SSN

Dwayne Dohmann, Factory Applications Engineer, Teradyne details how Teradyne is enabling Siemens SSN.

Technical Program Presentations

Tessent has a long history of presenting award-winning papers at ITC such as innovations in ATPG compression, 3D IC DFT, silicon lifecycle management and security.

Hardware root of trust for SSN-based DFT ecosystems

Hardware Root of Trust for SSN-based DFT ecosystems

Presented by:
J. Tyszer, B. Wlodarczak, Poznan University of Technology
J. Rajski, M. Trawka, Siemens Digital Industries Software

IEEE P1687.1 Extending the Network Boundaries for Test

M. Laisne, H. von Staudt, Dialog Semiconductor
A. Crouch, Amida Tech Solutions
M. Portolan, Univ Grenoble Alpes, CNRS
M. Keim, Siemens
B. Van Treuren, VT Enterprises
J. Rearick, Advanced Micro Devices
S. Zuo, Tailored Management

Industry Evaluation of Reversible Scan Chain Diagnosis

Industry Evaluation of Reversible Scan Chain Diagnosis
Presented by:
S. Urban, J. Janicki, M. Sharma, W-T. Cheng, Siemens EDA
M. Parley, K. Chung, S. Nicholson, S. Mittal, Qualcomm

Deterministic in-system test with X-masking

Deterministic in-system test with X-masking
Presented by:
J. Tyszer, B. Wlodarczak, Poznan University of Technology
G. Mrugalski, J. Rajski, Siemens Digital Industries Software

Test Generation for iterative design flow

Test Generation for an iterative design flow with RTL changes
Presented by:
J. Joe, I. Pomeranz, Purdue University
N. Mukherjee, J. Rajski, Siemens Digital Industries Software

Configurable BISR chain for fast repair data loading

Presented by:
W. Zou, B. Nadeau-Dostie, Siemens Digital Industries Software

IR-Drop Improvement with packet-based scan

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Poster PO.18: IR-Drop Improvement with packet-based scan presented by Joe Reynick, Tessent, Siemens and Srinivasulu Alampally, Broadcom.

DFT when designing tile-based/abutted physical blocks

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Poster PO.35: DFT considerations when designing tile-based/abutted physical blocks by Vidya Neerkundar, Tessent, Siemens.

Tessent Presentations

Learn from Tessent experts about recent advances in the Tessent products, and how you can best leverage these in your DFT implementation.

Tessent Streaming Scan Network

Deterministic on-chip compare and diagnosis Tessent Streaming Scan Network presented by Joe Reynick, Manager - Product Engineering, Tessent at Siemens EDA.

Using Tessent for tile-based design.

Using Tessent for tile-based design presented by Vidya Neerkundar, Product Manager, Tessent at Siemens EDA.

Tessent Embedded Analytics benefits for vehicle systems

Tessent Embedded Analytics - benefits for vehicle systems presented by Lee Harrison, Automotive Test Solutions, Tessent at Siemens EDA.

Key Tessent Presentations from ITC 2021

Don't miss this opportunity to look back and to learn from Tessent experts DFT presentations at ITC 2021.

3D IC test challenges, trends and solutions

Wu Yang, Technical & Foundry Programs Manager for Tessent at Siemens EDA, presents an EDA perspective on 3D IC test, including IEEE 1838 and 3D stack test methodology.

On reduction of deterministic test pattern sets

Janusz Rajski, Vice President of Research and Development for Tessent at Siemens EDA, presents work on the current state of pattern compaction technology.

Security and provisioning through test and safety

Lee Harrison, Automotive Test Solutions Manager for Tessent at Siemens EDA, explores the issues of security challenges in IC test.

Using SLM to monitor automotive electronics

Lee Harrison, Automotive Test Solutions Manager for Tessent at Siemens EDA, discusses using the tools of Silicon Lifecycle Management (SLM) to monitor the aging effects on automotive electronics.

Enhancing test on 3GHz designs with SSN

Srinu Alampally, Master Engineer at Broadcom, presents enhancing test on 3GHz designs with SSN.

SSN implementation on a large multi-die SOC

Dave Dehnert, Principal Engineer, Intel, discusses SSN implementation on a large multi-die SOC.

Samsung reference flow

Plug & Play DFT solutions to high performance computing (HPC)/AI presented on behalf of Dongkwan Han from Samsung Foundry.