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Tessent Embedded Analytics

RISC-V debug and trace

The Tessent Enhanced Trace Encoder is a market-leading solution for RISC-V, designed to meet the official RISC-V trace specification.

Real-time program execution monitoring

Access critical insights and forensic capabilities to manage the risk of building embedded systems with processor trace. The Tessent Enhanced Trace Encoder is a market-leading solution for RISC-V, designed to meet the official RISC-V trace specification.

This solution builds on the RISC-V standard produced by the Debug and Trace Working Group, which was led by representatives from Siemens who donated the trace algorithm to the RISC-V International community.

The Tessent Enhanced Trace Encoder goes well beyond the RISC-V standard. Get significant productivity gains in the development of complex systems, and access insights into each and every instruction since it is cycle accurate.

Fact Sheet

A complete trace solution for RISC-V processors

Complex systems are prone to imperfect software behaviors. Use our fully featured RISC-V trace solution, Tessent Enhanced Trace Encoder, to monitor the program execution of a CPU in real time.

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Case Study

How Seagate improves debug & optimization with Tessent

Listen to Richard Bohn, engineering director of advanced IP development at Seagate Technology, describe some of Seagate's challenges and how they use Tessent Embedded Analytics products to improve their debug and optimization.

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Fact Sheet

Tessent SystemInsight for SoC debug

Leverage our complete Eclipse-based integrated development environment (IDE) that extends the features of a traditional debugger (run control, trace). Get support for heterogeneous designs and full system visibility, which is enabled by the Tessent Embedded Analytics integrated into the system-on-chip (SoC).

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