RISC-V debug and trace

Many development teams and customers expect processor trace as a minimum feature of an SoC so their software developers can capture a record of executed instructions that can be used to reconstruct the exact execution sequence of their program. In 2018, the RISC-V community created the Efficient Trace (E-Trace) specification that would ensure compatibility across the RISC-V ecosystem, which included an efficient encoding scheme fit for the processors in the 21st century. The efficient encoding scheme allows developers to trace large amounts of data for longer time periods, allowing developers to understand program behavior, even in the most complex multicore systems. Tessent Embedded Analytics offers an industry-leading RISC-V E-Trace solution. 

Siemens involvement in RISC-V goes back to 2016 and the earliest days of the RISC-V Foundation (now RISC-V International); we were involved initially as UltraSoC, now as Siemens EDA. UltraSoC and Siemens made active and extensive contributions to the development of the RISC-V ecosystem, including key technical contributions to the RISC-V Efficient Trace (E-TRACE) standard. Our involvement continues today through the RISC-V Debug Trace and Performance Monitoring SIG. 

RISC-V was originally designed to support computer architecture research and education. The instruction set was started in May 2010 at the University of California, Berkeley in an open-source format.

Because of its open-source nature, developers could access and modify the processor architecture without licensing fees or restrictions. Companies took the opportunity to innovate with specialized hardware components for emerging applications at a time when demand was increasing exponentially, alongside safety concerns and power management. The ability of RISC-V-based SoCs to handle data and computation at large-scale has been particularly attractive to companies working in AI, data storage, 5G, automotive and security. Other companies are looking at RISC-V as a solution for low-cost embedded systems, such as edge IoT devices, sensors and actuators. 

The modular nature of the RISC-V instruction set architecture (ISA) allows chip designers to customize their devices for different markets and applications by selecting groups of instructions (ISA extensions). One of the ISA extension groups allows SoC designers and their customers to add their own custom instructions to accelerate their application, typically to speed up critical operations or code density. RISC-V custom instructions provide further invention and differentiation for companies in many highly competitive markets. This flexibility does pose some verification and validation challenges to ensure that the customization not just works, but also does not break anything else.

The Efficient RISC-V Trace specification includes the following mandatory features: 

• Instruction trace 
• Hart to encoder interface 
• Delta address trace mode 
• Efficient packet format 

Optional features (ISA extensions) include: 

• Multiple instruction retirement 
• Data trace 
• Implicit exception mode 
• Sequential inferable jump mode 
• Implicit return mode 
• Branch prediction mode 
• Jump target cache mode 
• Full address mode 
• Sign-based compression 
• XOR data trace compression 
• Differential data trace compression 
• Filtering 
• Timestamps 

The Tessent Enhanced Trace Encoder from Siemens EDA includes all the mandatory and optional features. It also includes:  

• Cycle-accurate trace