Catapult High-Level Synthesis Resource Library

This keynote examines how semiconductor design is changing to enable rapid development and deployment of custom, application-optimized, SoC designs – from concept to in-life operation, as we route to a sustainable compute future.

This talk will show how HLS can be used to quickly create and assess multiple RTL implementations for an AI accelerator from a single algorithmic description.

Delivering AI in today’s IoT systems efficiently goes beyond simply porting neural networks in Python to an edge device. Customized hardware built with High-Level Synthesis will differentiate your system from the competition.

Design flow including HW/SW co-design and HLS that allows developers to migrate compute intensive functions from SW running on an embedded processor to a HW based accelerator as a loosely coupled bus-based peripheral.

HLS Adoption for chip design is driven by increasing design & verification complexity and time to market pressures. HLS enables designers to get their chips to market faster by shortening the overall design & verification flow.

This session shows how to create different types of accelerators using HLS and how to integrate them into RISC-V processor designs. AI inferencing algorithm and an encryption algorithm will be used as examples.

This paper describes the design and deployment, at scale, of a new accelerator targeted at warehouse-scale video transcoding. The state-of-the-art hardware design flow adopted in the VCU development used Catapult. See section 3.4.

This on-demand training learning path introduces engineers to C++, HLS and the use of Catapult for hardware design.

This on-demand training learning path introduces users to the design concepts needed for HLS design, debug, and verification using SystemC and the MatchLib library.

This learning path introduces users to the Catapult HLV flow, enabling rigorous functional verification of high-level source using known and trusted techniques.

Design flow including HW/SW co-design and HLS that allows developers to migrate compute intensive functions from SW running on an embedded processor to a HW based accelerator as a loosely coupled bus-based peripheral.

HLS Adoption for chip design is driven by increasing design & verification complexity and time to market pressures. HLS enables designers to get their chips to market faster by shortening the overall design & verification flow.

This seminar uses an AXI-based AI/ML accelerator to demonstrate how HLS can rapidly go from an algorithm, through C-based design, system-level performance analysis, and comprehensive verification with RTL coverage closure.

Introduction and technical details to understand how HLS rapidly and accurately explores power/performance of their algorithms, quickly get to FPGA implementations to create demonstrator/prototypes and more.

This 8 part technical seminar is designed for those that know very little about HLS and those familiar with its concepts, but want real examples applying it to computer vision and deep learning implementation.

The following video series provides an introduction into designing simple ML accelerators using HLS.

This 5-part series provides a step-by-step walkthrough of how to use Catapult Design Analyzer to analyze and visualize synthesis results, automatically identify coding style mistakes, and pinpoint optimization bottlenecks.

This 9-part video series provides a step-by-step walkthrough of what is needed to take a C++ floating-point algorithm all the way to optimized RTL using Catapult High-Level Synthesis.