Catapult Coverage

Catapult Coverage provides HLS-aware code coverage, including statement, branch, condition, FEC and array access coverage, for C++/SystemC HLS designs. It also provides SV-inspired functional coverage with support for covergroups, coverpoints, bins and crosses within C++/SystemC test benches.

KEY FEATURES

An efficient approach to metrics driven HLV

Use traditional RTL metrics such as statement, branch, condition and expression coverage, combined with SystemVerilog-inspired functional coverage to achieve high quality HLS-aware coverage prior to High-Level Synthesis.

C++/SystemC simulation executes 100’s of times faster than RTL simulation, enabling comprehensive verification of high-level system behavior. Catapult Coverage complements high level simulation with traditional RTL metrics such as statement, branch, condition and expression code coverage along with SystemVerilog-inspired functional coverage.

Catapult on-demand training

The Catapult High-Level Synthesis (HLS) on-demand training library contains a set of learning paths with modules to introduce engineers to HLS and high-level verification.

High-Level Synthesis and Verification Group

A group to discuss the finer points of design and verification using Siemens EDA HLS and HLV tools. Join the discussion on new topics, features, content and technical experts.

HLSLibs

A free and open set of libraries implemented in standard C++ for bit-accurate hardware and software design. It's an open community for exchange of knowledge and IP for HLS that can be used to accelerate both research and design.

HLS Design and Verification Blog

Blog covering next generation high-level synthesis (HLS) design and verification methodologies and techniques.

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Catapult Support

Access detailed documentation, releases, resources and more.

EDA consulting

Helping you achieve maximum business impact by addressing complex technology and enterprise challenges with a unique blend of development and design experience and methodology expertise.