Reliability verification helps ensure the robustness of an IC design by considering the context of schematic and layout information to perform checks against various electrical and physical design rules that reduce susceptibility to premature or catastrophic electrical failures, usually over time.
Calibre reliability verification ensures designs are protected against early device failure and long-term performance degradation. A novel logic-driven layout analysis combines schematic and layout parameters for precise, accurate analysis of complex reliability concerns not possible with traditional verification tools.
Design verification that helps ensure the robustness of a design and reduce susceptibility to premature or catastrophic electrical failures by considering the context of schematic and layout information