The Calibre DesignEnhancer platform offers P&R and custom/analog design teams a fast, integrated environment for implementing design modifications that reduce IR drop and EM and prepare layouts for physical verification, with Calibre confidence in the results.
The Calibre DesignEnhancer via layout modification (Via) use model automatically adds correct-by-construction DRC-clean vias to moderate the impact of via resistance on manufacturing robustness and reliability, as well as reduce EM and IR drop effects.
The Calibre DesignEnhancer power grid enhancement (Pge) use model eliminates or reduces IR drop and EM issues by taking advantage of open space to insert Calibre-clean metal and vias that create parallel run lengths to lower resistance on power grid structures.
The Calibre DesignEnhancer physical verification readiness (Pvr) use model uses proven Calibre functionality to deliver correct-by-construction filler cell and DCAP cell insertion in IC layouts after design implementation.
We help you adopt, deploy, customize and optimize your complex design environments. Direct access to engineering and product development lets us tap into deep domain and subject matter expertise.
The Siemens Support Center provides you with everything in one easy-to-use location -
knowledgebase, product updates, documentation, support cases, license/order information and more.
Across all process nodes and design styles, the Calibre toolsuite delivers accurate, efficient, comprehensive IC verification and optimization, while minimizing resource usage and tapeout schedules.