Overview
Calibre DesignEnhancer design-stage IC optimization
Calibre DesignEnhancer automated layout optimizations enable design teams to quickly and easily apply analysis-based, Calibre signoff-quality layout optimizations during IC design or implementation to improve design reliability and manufacturability.
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Fast signoff-quality design-stage layout optimization
The Calibre DesignEnhancer platform offers P&R and custom/analog design teams a fast, integrated environment for implementing design modifications that reduce IR drop and EM and prepare layouts for physical verification, with Calibre confidence in the results.
Automated via insertion
The Calibre DesignEnhancer via layout modification (Via) use model automatically adds correct-by-construction DRC-clean vias to moderate the impact of via resistance on manufacturing robustness and reliability, as well as reduce EM and IR drop effects.
Automated insertion of metal and vias in open areas
The Calibre DesignEnhancer power grid enhancement (Pge) use model eliminates or reduces IR drop and EM issues by taking advantage of open space to insert Calibre-clean metal and vias that create parallel run lengths to lower resistance on power grid structures.
Automated filler cell and DCAP cell insertion
The Calibre DesignEnhancer physical verification readiness (Pvr) use model uses proven Calibre functionality to deliver correct-by-construction filler cell and DCAP cell insertion in IC layouts after design implementation.
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