As integrated circuit (IC) designs grow in complexity, traditional methods of design rule check (DRC) struggle to keep pace with modern demands. Initially tailored for simpler, custom layouts, traditional DRC workflows use an iterative “construct by correction” approach. However, as automation, advanced IC tools, and multi-layered design hierarchies become standard, relying on sequential DRC methods often results in prolonged runtimes and inefficient resource use.
The Siemens Calibre platform delivers innovative physical verification solutions, including Calibre nmDRC Recon, which employs a proactive “shift-left” approach. By shifting verification tasks earlier in the design process, this IC tool significantly reduces debug time, facilitates incomplete data handling, and accelerates the path to tape-out. This paper examines the advantages of the shift-left methodology and demonstrates how a customer utilized Calibre nmDRC Recon to achieve faster DRC cycles, comprehensive design rule check coverage, and optimized compute hardware for more efficient physical verification.
