The Calibre nmDRC Recon technology reduces iteration and debug time by minimizing the rules and data required for DRC in early design iterations. Results are displayed as color maps to quickly identify root causes of failures, reducing runtime, debug time, and the total number of DRC iterations.
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Design teams are under continuous pressure to reduce time to market, but verification cycles are only getting longer and more difficult for designs at all nodes. The Calibre nmDRC Recon tool provides focused DRC to dramatically speed up early design analysis and reduce overall design closure time.
DRC rules requiring extensive context often run slowly and produce millions of errors in the face of systemic layout issues. The Calibre nmDRC Recon technology selects rules of a local scope, speeding runtimes and generating results that are geometrically close to the source of the issue, reducing debug.
Block and top-level routing are often designed in parallel. Verifying routing while blocks are incomplete leads to long runtimes and confusing results. The Calibre nmDRC Recon gray box feature enables removal of block-specific data as needed to reduce check time and error results from the block, while still enabling checking in context.
Results Heat Map
The Calibre nmDRC Analyze feature generates a color map of DRC results. Because the Calibre nmDRC Recon technology focuses on checks with a local scope, reviewing regions with high result counts can help quickly identify a root cause. Many errors can often be eliminated with simple floorplan or placement corrections, speeding debug and iteration time.
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Across all process nodes and design styles, the Calibre toolsuite delivers accurate, efficient, comprehensive IC verification and optimization, while minimizing resource usage and tapeout schedules.