Heterogeneous and homogeneous 2.5/3D IC package connectivity planning and prototyping for system technology co-optimization.
Package assembly logical connectivity can be constructed by using full or partial graphical schematics, useful for high device count designs such as SiP modules and/or the re-use/retargeting of previous designs.
System connectivity management, visualization, and system-level logical verification of multi-die, multi-component, and multi-substrate IC package designs.
Xpedition Substrate Integrator integrates die, chiplets, and interposers from different process nodes and suppliers. Multiple formats are supported including LEF/DEF, GDS, AIF, and CSV/TXT. Hierarchical virtual die models support bidirectional ECO changes of objects under design/optimization.
Cross-substrate planning and co-optimization greatly improve predictability during implementation by finding and fixing issues before they become late-stage surprises. A system perspective with cross-substrate visibility improves communication and coordination through immediate feedback to decisions typically made on an individual substrate basis.
Provides an early exploration of SI performance during design planning and co-optimization allowing designers to explore multiple SI scenarios very early in the process while the cost of change is low. Prevents potential issues from reaching implementation causing delays and rework.
This verification solution provides extensive and comprehensive capabilities across every level of the package assembly through direct digital integration with Calibre 3DSTACK. By using the actual planned manufacturing data, as opposed to the design tools native database, you ensure that post-processing errors are not introduced.