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{"heading":"Package Simulation","shareURL":"https://eda.sw.siemens.com/en-US/ic-packaging/software/package-simulation/features/","children":"<p>Comprehensive analysis of die/package coupling, signal integrity/PDN performance, and thermal conditions. SI/PDN issues are found, investigated, and validated. 3D thermal modeling and analysis predict airflow and heat transfer in and around electronic systems.</p>"}

Package Simulation

<p>Comprehensive analysis of die/package coupling, signal integrity/PDN performance, and thermal conditions. SI/PDN issues are found, investigated, and validated. 3D thermal modeling and analysis predict airflow and heat transfer in and around electronic systems.</p>
{"items":[{"title":"Analysis of Voltage Drop & IC Switching Noises","description":"<p>Power distribution networks can be analyzed for voltage drop and switching noise issues. Identify potential DC power delivery issues such as excessive voltage drop, high current densities, excessive via currents and associated temperature rise including co-simulation for signal/power/thermal impact. Results can be reviewed in graphical and report formats.</p>","button":{"text":"Read Fact Sheet","url":"https://resources.sw.siemens.com/en-US/fact-sheet-power-integrity-analysis"},"image":"https://images.sw.cdn.siemens.com/siemens-disw-assets/public/7bZFYv0G1R6QpwfYctR3hH/en-US/analysis-of-voltage-drop-promo-640x480.jpg?w=640&q=60","imageAlt":"analysis-of-voltage-drop-promo","imageTitle":"analysis-of-voltage-drop-promo","rightIcon":"fal fa-long-arrow-right fa-lg"},{"title":"Analysis SI Issues in the Design Cycle","description":"<p>HyperLynx SI supports general-purpose SI, DDR interface signal integrity and timing analysis, power-aware analysis, and compliance analysis for popular SerDes protocols. From pre-route design exploration and “what-if” analysis through detailed verification and sign-off, all with fast, interactive analysis, ease-of-use, and integration with Package Designer.</p>","button":{"text":"Read Fact Sheet","url":"https://resources.sw.siemens.com/en-US/fact-sheet-hyperlynx-signal-integrity"},"image":"https://images.sw.cdn.siemens.com/siemens-disw-assets/public/4Fo86lsUYgbf6n2p9c7Dns/en-US/analysis-si-promo-640x480.jpg?w=640&q=60","imageAlt":"analysis-si-promo","imageTitle":"analysis-si-promo","rightIcon":"fal fa-long-arrow-right fa-lg"},{"title":"Comprehensive SERDES Analysis","description":"<p>SERDES interface analysis and optimization include FastEye diagram analysis, S-parameter simulation, and BER prediction. These utilize automatic channel extraction, interface-level channel compliance verification, and pre-layout design exploration. Together, these automate SERDES channel analysis while retaining accuracy.</p>","button":{"text":"Read Fact Sheet","url":"https://resources.sw.siemens.com/en-US/fact-sheet-hyperlynx-serdes-analysis"},"image":"https://images.sw.cdn.siemens.com/siemens-disw-assets/public/2AcCBtqV68yEbonLsyvax8/en-US/serdes-promo-640x480.jpg?w=640&q=60","imageAlt":"SERDES","imageTitle":"SERDES","rightIcon":"fal fa-long-arrow-right fa-lg"},{"title":"Intra-die & Inter-die Parasitic Extraction","description":"<p>For an analog design, the designer must simulate the system circuitry, including parasitics. For a digital design, the designer must run static timing analysis (STA) on the complete package assembly, including parasitics. Calibre xACT provides accurate parasitic extraction of TSVs, front and backside metal, and TSV to RDL coupling.</p>","button":{"text":"Read White Paper","url":"https://resources.sw.siemens.com/en-US/white-paper-advancing-the-art-of-parasitic-extraction-the-calibre-xact-platform"},"image":"https://images.sw.cdn.siemens.com/siemens-disw-assets/public/1gbJingrY3diemr0aDwvg9/en-US/xact-promo-640x480.jpg?w=640&q=60","imageAlt":"xact","imageTitle":"xact","rightIcon":"fal fa-long-arrow-right fa-lg"},{"title":"Full-3D Electro-magnetic-quasi-static (EMQS) Extraction","description":"<p>Full package model creation with multi-processing for faster turnaround time. It is ideally suited for power integrity, low-frequency SSN/SSO, and complete-system SPICE model generation while accounting for skin effect impact on resistance and inductance. As an integral part of Xpedition Substrate Designer, it is immediately available to all package designers.</p>","button":{"text":"Watch Video","url":"https://resources.sw.siemens.com/en-US/technology-overview-new-in-hyperlynx-advanced-solvers"},"image":"https://images.sw.cdn.siemens.com/siemens-disw-assets/public/3eDXcUd0zh62oC6ierDnvs/en-US/full-3d-emqs-promo-640x480.jpg?w=640&q=60","imageAlt":"full 3d","imageTitle":"full 3d","rightIcon":"fal fa-long-arrow-right fa-lg"},{"title":"2.5/3D IC Package Thermal Modeling","description":"<p>Modeling heterogeneous 2.5/3D IC-package thermal chip-package-interactions is important for several reasons. Designing a large high power device, e.g. a AI or HPC processor without considering how to get the heat out is likely to lead to problems later on, resulting in a sub-optimal packaging solution from cost, size, weight and performance perspectives.</p>","button":{"text":"Learn More","url":"https://www.plm.automation.siemens.com/global/en/products/simcenter/flotherm-xt.html"},"image":"https://images.sw.cdn.siemens.com/siemens-disw-assets/public/gH9pbG8eC8PfFRohFrzXW/en-US/2.5-3dic-packaging-thermal-modeling-promo-640x480.jpg?w=640&q=60","imageAlt":"2.5-3dic-packaging-thermal-modeling Image","imageTitle":"2.5-3dic-packaging-thermal-modeling Image","rightIcon":"fal fa-long-arrow-right fa-lg"}],"env":"master","locale":"en-US"}

Analysis of Voltage Drop & IC Switching Noises

<p>Power distribution networks can be analyzed for voltage drop and switching noise issues. Identify potential DC power delivery issues such as excessive voltage drop, high current densities, excessive via currents and associated temperature rise including co-simulation for signal/power/thermal impact. Results can be reviewed in graphical and report formats.</p>

analysis-of-voltage-drop-promo

Analysis SI Issues in the Design Cycle

<p>HyperLynx SI supports general-purpose SI, DDR interface signal integrity and timing analysis, power-aware analysis, and compliance analysis for popular SerDes protocols. From pre-route design exploration and “what-if” analysis through detailed verification and sign-off, all with fast, interactive analysis, ease-of-use, and integration with Package Designer.</p>

analysis-si-promo

Comprehensive SERDES Analysis

<p>SERDES interface analysis and optimization include FastEye diagram analysis, S-parameter simulation, and BER prediction. These utilize automatic channel extraction, interface-level channel compliance verification, and pre-layout design exploration. Together, these automate SERDES channel analysis while retaining accuracy.</p>

SERDES

Intra-die & Inter-die Parasitic Extraction

<p>For an analog design, the designer must simulate the system circuitry, including parasitics. For a digital design, the designer must run static timing analysis (STA) on the complete package assembly, including parasitics. Calibre xACT provides accurate parasitic extraction of TSVs, front and backside metal, and TSV to RDL coupling.</p>

xact

Full-3D Electro-magnetic-quasi-static (EMQS) Extraction

<p>Full package model creation with multi-processing for faster turnaround time. It is ideally suited for power integrity, low-frequency SSN/SSO, and complete-system SPICE model generation while accounting for skin effect impact on resistance and inductance. As an integral part of Xpedition Substrate Designer, it is immediately available to all package designers.</p>

full 3d

2.5/3D IC Package Thermal Modeling

<p>Modeling heterogeneous 2.5/3D IC-package thermal chip-package-interactions is important for several reasons. Designing a large high power device, e.g. a AI or HPC processor without considering how to get the heat out is likely to lead to problems later on, resulting in a sub-optimal packaging solution from cost, size, weight and performance perspectives.</p>

2.5-3dic-packaging-thermal-modeling Image