Design verification of multiple die and substrate assemblies by identifying geometries per layer per die placement in the assembly. DRC and LVS is performed on the interface geometries with support for dies from multiple processes.
Next-generation packaging solutions require proven, automated sign-off for physical, electrical, thermal, and manufacturing performance within a single environment that enables designers to manage all of these processes in an efficient, repeatable, and automated flow. Utilizing Calibre and HyperLynx for verification, designers can both identify and resolve problems before final sign-off.
Equation-based DRC technology (eqDRC) brings user extensibility and fast runtimes to a whole host of complex design and process interactions. eqDRC enables precise and accurate characterizations of complex, multi-variable, and non-Manhattan geometries, as well as 2D/3D interactions that have a direct impact on performance and/or manufacturability.
Provides complete design verification of stacked die assemblies. Delivers 3D assembly LVS for assemblies such as stacked memories, stacked sensor arrays, interposer-based structures, or package-level RDL routing. Errors/issues cross probed directly into design for immediate attention. Driven by the Xpedition Substrate Integrators 3D assembly model.
Maximize your design to manufacturing efficiencies by leveraging the integration with Valor technology. Identify potential manufacturing issues while you are still in the organic substrate design stage. And to further streamline the process, you can define various stages of the design process, each with their own list of DFM checks relevant to that stage.