HyperLynx AC PDN Design and Verification

An ideal capacitor model has no parasitic inductance (ESL) or parasitic resistance (ESR). In practice, all components will have some level of parasitics that will affect the behavior and must be accounted for. The RLC circuit model is an accurate method of modeling the impedance of a decoupling capacitor.

The RLC circuit model introduces self-resonant frequency (SRF) which depends on the capacitance and inductance of the component. Below the SRF, the impedance is dominated by capacitance and has a negative sloped curve with impedance decreasing with frequency. Above the SRF, the impedance is dominated by inductance and the curve has a positive slope with impedance increasing with frequency. In order to reduce high-frequency impedance, the inductance of the capacitor should be minimized.

Decoupling capacitors placed on the PDN can have non-intuitive behavior at times. Decaps with identical capacitance values mounted in parallel maintain the same self-resonant frequency (SRF) point and reduce the overall impedance. In contrast, mounting capacitor parts with differing values in parallel can cause parallel resonant frequency (PRF) points due to the interaction between capacitors with different SRF points. PRF points are important because they cause high impedance peaks in the PDN profile.

It is important to consider the low frequency interaction with the VRM and bulk capacitors, as well as the higher frequency interaction with the inter-plane capacitance of the board as well as any package or on-die capacitance – the behavior of these combined interactions is extremely difficult to approximate manually. With HyperLynx Advanced Decoupling, all components of the PDN can be modeled effectively and the full behavior of the PDN verified and optimized.

HyperLynx advanced decoupling has industry leading analysis speed and database capacity, is easy to use with automated workflows, includes comprehensive reporting, and optionally includes the PDN Decoupling Optimizer which can be used to efficiently optimize a design for increased margin, reduced cost or part count, or increased physical routing space.

HyperLynx advanced decoupling analysis evaluates the ability of a PDN to provide low-impedance paths for specific power supply pin pairs or pin group pairs. Advanced distributed PDN decoupling simulation accounts for the location of each decoupling capacitor, inter-plane capacitance and inductance, the board outline, and the mounting parasitics and loss for decoupling capacitors.