The inclusion of multiple embedded processors and advanced interconnect systems, increasing software content, more functionality, and the configurability required by multi-platform based designs all require a functional verification solution that unifies a broad arsenal of verification solutions.
Auto-generated coverage models speed testbench programming for big gains in verification productivity while verification management reduces the time to perform regression testing and merge coverage results from hours to minutes.
Formal technologies root out obscure bugs through exhaustive analysis. Several specialized formal solutions complement simulation, boosting productivity by targeting verification tasks that are otherwise difficult to complete.
Comprehensive verification and verification management reduce the risk of validating complex automotive designs and provide insight for coverage and metric driven flows required to satisfy ISO 26262.
Debug is one of the most important verification technologies and is critical for achieving productivity in today's complex designs. Debug tools must provide maximum performance, capacity and automation.
UVM provides essential information about the operation of dynamic class-based testbenches in the familiar contexts of source code and waveform viewing, making it easier to understand the operation of verification environments.
Power management verification in low power designs requires a comprehensive solution for verifying power management architectures, clock-domain crossings, power control logic, and power management in analog/mixed-signal designs.
The Questa Verification Solution continues to evolve in response to the growing complexity of SoC designs. The increasing software content and configurability required by multi-platform based designs require a functional verification solution that unifies a broad arsenal of verification solutions.