Siemens EDA events and webinars

Don't miss this live webinar, introducing & demonstrating the new Tessent Multi-die software that delivers comprehensive automation for the highly complex DFT tasks associated with the latest 2.5D and 3D IC designs.

Learn how C++ and SystemC/MatchLib HLS is more than just converting SystemC to RTL. We’ll cover language choice, architecture exploration, power estimation and optimization that all work to deliver competitive RTL fast & cheap.

Learn how to design low-power, IPs/SOCs by including low-power techniques in your design flows and tracking power throughout the RTL development cycle to realize energy efficient designs. 

Join this live webinar in which Peter Shields, Product Manager, Tessent, provides an expert insight on the RISC-V trace standard and demonstrates how implementing the standard helps reduce the risks of adopting RISC-V. 

Join Calibre IC Manufacturing at SPIE Advanced Lithography 2023 at the San Jose Convention Center in San Jose, CA. Siemens EDA will be presenting 16 papers.

Attend our informative technical keynote, tutorial, workshops, papers, and poster sessions and visit our exhibit booth to learn how Siemens can help you engineer a smarter future faster.

Demonstrating why early RTL power and energy estimations are key metrics and how the two metrics have taken a center stage lately in performance-sensitive system design considerations.

Tutorial will show how to verify a machine learning algorithm from Python code in a machine learning framework, like TensorFlow or Caffe, to RTL. The algorithm will be migrated from Python, to C++, and finally to RTL using HLS.

Find out more about the webinar "Architectural Improvements for Low-Power and Functional Safety of Dataflow CNN Accelerators Using HLS".

Attend one our EDA technical sessions to learn more about Xpedition IC Packaging design. We will be showcasing and discussing our comprehensive solutions and workflows for 2.5/3D heterogeneous semiconductor packaging integration.

We will showcase our advanced HyperLynx technologies for electrical sign-off, including a complete analysis environment for SerDes Channel compliance, DDRx designs, full-wave 3D electromagnetic modeling, DRC, and power integrity.

Attend one our EDA technical sessions to learn more about Xpedition IC Packaging design. We will be showcasing and discussing our comprehensive solutions and workflows for 2.5/3D heterogeneous semiconductor packaging integration.

Siemens is driving transformation to enable a digital enterprise for electronic systems. We will be showcasing and discussing our comprehensive solutions and workflows for 2.5/3D heterogeneous semiconductor packaging integration.

Design flow including HW/SW co-design and HLS that allows developers to migrate compute intensive functions from SW running on an embedded processor to a HW based accelerator as a loosely coupled bus-based peripheral.

Learn how you can use High-Level Synthesis to go from Python to synthesizable RTL to deploy a custom AI accelerator faster and easier than you thought possible. 

osmosis is about sharing success in using formal techniques to solve IC verification challenges and networking with our R&D experts and piers in the IC verification field

PLDA and Siemens EDA join to introduce you to PCIe 6.0, including architecture differences from prior generations, performance improvements, and how PCIe 6.0 compares from both a designer and verification perspective.

Join the online platform to learn how we collaborate with TSMC and mutual customers to develop innovative EDA technology.

Cornell intros HiSparse: accelerator on sparse-matrix dense-vector multiplication. Using both HLS implementation and simulation, their sparse accelerators deliver promising speedup with increased bandwidth and energy efficiency.

FNAL demos that a NN autoencoder model can be implemented in a radiation-tolerant ASIC to perform lossy data compression. This alleviates the data transmission problem while preserving the detector energy profile's critical info.

Access key presentations from Tessent, customers & partners at ITC 2022.

Along with its associated workshops & tutorials, ITC is the place to discover new DFT technologies, IC test, yield learning & in-life monitoring & analytics.