Tessent Yield Learning
Tessent SiliconInsight
Tessent SiliconInsight provides an automated interactive environment for test bring-up, debug, and silicon characterization of devices containing Tessent ATPG, EDT, BIST, and/or IJTAG test structures.
Why Tessent SiliconInsight?
Greatly increase productivity during silicon validation and debug, speeding time-to-market. The Tessent SiliconInsight solution works in a bench-top environment and connects to any debug, performance, or bring-up board, accessing up to 120 device pins.
Validate test patterns before first silicon
Validate test patterns before first silicon using the design in a standard simulator, inject faults, characterize potential failure scenarios without silicon.
Low-cost, high-availability characterization
Desktop debug environment for ATPG, MBIST, LBIST, and IJTAG through access to up to 120 device pins using 3rd party USB adaptors. Shmoo capability of power and clock through GPIB.
Link the power of IJTAG with ATE
The ATE-Connect technology creates an industry-standard interface to eliminate communication barriers between proprietary, tester-specific software and design-for-test (DFT) platforms.
Accelerating pattern bring-up on high pin count designs
Listen as Ari Krantz, DFT Engineer at Broadcom, discusses accelerating pattern bring-up on high pin count designs, an industrial case study using SiliconInsight-HP beta.
Overcome yield barriers with PDF Solutions and Siemens
Breaking through yield barriers and accelerating yield ramp calls for new solutions that leverage the best technologies on the market. In this webinar, Siemens and PDF Solutions technologists introduce an integrated, comprehensive end-to-end solution that includes analytics, scan diagnosis, and machine learning.
