Precision Hi-Rel, enhances Precision RTL Plus with automated mitigation of SEUs/SETs in safety-critical & high-reliability applications using TMR, safe FSM and other optimizations.
Precision Hi-Rel offers multiple SEE mitigation strategies for safety-critical and high-reliability applications. Integration with FormalPro LEC provides assurance that synthesis-based mitigated design is functionally equivalent to the RTL, ensuring DO-254 certification.
TMR is the most popular mitigation strategy used for protection from SEUs/SETs in FPGAs. Precision Hi-Rel provides the widest selection of TMR modes - LTMR, DTMR, GTMR & intelligent Selective TMR (iSTMR), enabling users to trade-off between safety, area and performance. Inserting TMR at the synthesis level provides greater user control and superior QoR.
Precision Hi-Rel offers two enhanced safe FSM modes:
With seamless integration in the synthesis flow and full user-control, it allows designers to implement these FSM optimizations globally or at modular level.
Precision Hi-Rel gives you the option of a push-button flow for mitigation strategies or a user-directed flow for selective mitigation. User-directed mitigation is implemented using pragmas/attributes in HDL or constraints in TCL.
FormalPro and Precision Hi-Rel is the industry’s only integration that proves functional equivalence between RTL and the mitigated FPGA design. An FVI setup file, containing synthesis optimization and mitigation information, is auto-generated by Precision, enabling a reliable push-button RTL to gate netlist to mitigated gate netlist equivalence checking.
Industry’s only fully-automated synthesis-based solution in Precision Hi-Rel identifies and applies selective TMR intelligently on portions of the design that are more susceptible to SEEs and where FPGA resources are limited.
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