Precision Hi-Rel

Precision Hi-Rel, enhances Precision RTL Plus with automated mitigation of SEUs/SETs in safety-critical & high-reliability applications using TMR, safe FSM and other optimizations.


Mitigate SEEs and Ensure Functional Equivalence

Precision Hi-Rel offers multiple SEE mitigation strategies for safety-critical and high-reliability applications. Integration with FormalPro LEC provides assurance that synthesis-based mitigated design is functionally equivalent to the RTL, ensuring DO-254 certification.


Triple Modular Redundancy (TMR)

TMR is the most popular mitigation strategy used for protection from SEUs/SETs in FPGAs. Precision Hi-Rel provides the widest selection of TMR modes - LTMR, DTMR, GTMR & intelligent Selective TMR (iSTMR), enabling users to trade-off between safety, area and performance. Inserting TMR at the synthesis level provides greater user control and superior QoR.



Safe FSM

Precision Hi-Rel offers two enhanced safe FSM modes:

  • SEU detect - detects invalid transition/state and recovers to a known state
  • SEU tolerant - absorbs an SEU and continues operation without interruption

With seamless integration in the synthesis flow and full user-control, it allows designers to implement these FSM optimizations globally or at modular level.



Push-button or User-directed Mitigation Flow

Precision Hi-Rel gives you the option of a push-button flow for mitigation strategies or a user-directed flow for selective mitigation. User-directed mitigation is implemented using pragmas/attributes in HDL or constraints in TCL.


Equivalence checking with FormalPro

FormalPro and Precision Hi-Rel is the industry’s only integration that proves functional equivalence between RTL and the mitigated FPGA design. An FVI setup file, containing synthesis optimization and mitigation information, is auto-generated by Precision, enabling a reliable push-button RTL to gate netlist to mitigated gate netlist equivalence checking.


Precision Hi-Rel: Intelligent Selective TMR (iSTMR)

Industry’s only fully-automated synthesis-based solution in Precision Hi-Rel identifies and applies selective TMR intelligently on portions of the design that are more susceptible to SEEs and where FPGA resources are limited.

Siemens groundbreaking FPGA synthesis solution offers SEE (Single Event Effects) mitigation for safety-critical and high-reliability designs, supporting multiple vendors. It provides multiple automated & user-controlled mitigation strategies for mil-aero, space, automotive, and medical applications.

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