Precision Hi-Rel
Siemens groundbreaking FPGA synthesis solution offers SEE (Single Event Effects) mitigation for safety-critical and high-reliability designs, supporting multiple vendors. It provides multiple automated & user-controlled mitigation strategies for mil-aero, space, automotive, and medical applications.
Mitigate SEEs & Ensure Functional Equivalence
For safety-critical and high-reliability applications, Precision Hi-Rel offers industry’s most comprehensive SEE mitigation strategies. And, integration with FormalPro provides assurance that synthesis-based mitigated design is functionally equivalent to the RTL, ensuring DO-254 certification.
TMR is the most popular mitigation strategy used for protection from SEUs/SETs in FPGAs. Precision Hi-Rel provides the widest selection of TMR modes - LTMR, DTMR, GTMR & intelligent Selective TMR (iSTMR), enabling users the trade-off between safety, area, and performance. Inserting TMR at the synthesis level provides greater user control and superior QoR.\n\n
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SEU Detect - detects invalid transition/state and recovers to a known state
SEU Tolerant - absorbs an SEU and continues operation without interruption
With seamless integration in the synthesis flow and full user-control, it allows designers to implement these FSM optimizations globally or at a modular level.\n\n\n\n\n\n\r
\r
","image":"//images.ctfassets.net/17si5cpawjzf/6GRZmqq3uwKTOSGuPWPM8c/096dee189bf01e235cd9fc9cc4ab582a/safe-fsm-promo-640x480.jpg?w=640&q=60","rightIcon":"fal fa-long-arrow-right fa-lg"},{"title":"Equivalence Checking with FormalPro","subtitle":"Functional Equivalence ","description":"FormalPro and Precision Hi-Rel is the industry’s only integration that proves functional equivalence between RTL and the mitigated FPGA design. An FVI setup file, containing synthesis optimization and mitigation information, is auto-generated by Precision, enabling a reliable push-button RTL to gate netlist to mitigated gate netlist equivalence checking.
","image":"//images.ctfassets.net/17si5cpawjzf/3sOYe4dXPrBMfKjKvxxtfo/ca52c411955d6f08ff9cf11e1832f8a5/functional-equivalence-promo-640x480.jpg?w=640&q=60","rightIcon":"fal fa-long-arrow-right fa-lg"}],"env":"master"}Mitigate SEEs
Triple Modular Redundancy (TMR)
TMR is the most popular mitigation strategy used for protection from SEUs/SETs in FPGAs. Precision Hi-Rel provides the widest selection of TMR modes - LTMR, DTMR, GTMR & intelligent Selective TMR (iSTMR), enabling users the trade-off between safety, area, and performance. Inserting TMR at the synthesis level provides greater user control and superior QoR.
Protect FSMs
Safe FSM
Precision Hi-Rel offers two enhanced safe FSM modes:
SEU Detect - detects invalid transition/state and recovers to a known state
SEU Tolerant - absorbs an SEU and continues operation without interruption
With seamless integration in the synthesis flow and full user-control, it allows designers to implement these FSM optimizations globally or at a modular level.
Functional Equivalence
Equivalence Checking with FormalPro
FormalPro and Precision Hi-Rel is the industry’s only integration that proves functional equivalence between RTL and the mitigated FPGA design. An FVI setup file, containing synthesis optimization and mitigation information, is auto-generated by Precision, enabling a reliable push-button RTL to gate netlist to mitigated gate netlist equivalence checking.
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