PowerPro Power Analysis & Optimization Resource Library

Best practices for applying RTL power optimization are essential for realizing low-power, energy efficient designs and can help you meet power budgets, mitigate potential reliability issues and discover thermal issues early.

Learn how to design low-power, IPs/SOCs by including low-power techniques in your design flows and tracking power throughout the RTL development cycle to realize energy efficient designs. 

This seminar presents an effective hardware design methodology to build lowest power RTL IP and/or designs. A combination of technical sessions and case studies delivered by industry leaders in low power chips: ARM and Cisco.

This on-demand training learning path introduces engineers to PowerPro basics and will teach how to read a design to analyze for power or optimizations.

This on-demand training learning path introduces engineers to PowerPro basics and will teach how to read a design to analyze for power or optimizations.

SWPP is a simple, effective approach that can be applied to a wide range of other low-power design projects. Jointly developed with Samsung, this method has the potential to improve decision-making in the low-power design process.

To estimate power accurately, Veloce Streaming API with PowerPro was used to accurately estimate power for key time windows of end-user software with entire SoC. This methodology enables to understand our power/energy status early

A statistical approach is presented that helps identify the combinational clusters that are contributing to excessive power consumption in the design. PowerPro can help identify these issues upfront in the design cycle.

This proposal presents a new methodology for reducing clock tree power at the RTL design level using fine-grained CTS data analytics. This methodology enables significant power savings which is proven by included results.

Learn how to design low-power, IPs/SOCs by including low-power techniques in your design flows and tracking power throughout the RTL development cycle to realize energy efficient designs. 

Demonstrating why early RTL power and energy estimations are key metrics and how the two metrics have taken a center stage lately in performance-sensitive system design considerations.

In this session we will present a recommended use model in which power is addressed early. This approach yields better results in terms of power saving impact and time-to-power.

This seminar presents an effective hardware design methodology to build lowest power RTL IP and/or designs. A combination of technical sessions and case studies delivered by industry leaders in low power chips: ARM and Cisco.

A methodology to estimate the power dissipation of an end-user application on the Register Transfer Level (RTL) model of the target SoC platform is presented. 

Automated Input Qualification Methodology proposed performing various Data Integrity Checks at design build & prototype stage ensuring quicker iterations that input data is high fidelity leading to well correlated power numbers.

Input Qualification Methodology Helps Achieve System Level Power Numbers 8x Faster:
It performs various Data Integrity Checks at design build and prototype stage and ensures in quicker iterations that input data is high fidelity.