Multi-core architecture that computes power in parallel allows an incremental Power Analysis flow that lets the designs to be compiled once and reused multiple times with different stimuli. The combination of incremental run and highly parallelized power computation delivers extremely fast results.
PowerPro utilizes Oasys synthesis under-the-hood to build a prototype of the design which coupled with physical awareness, provides accurate, out-of-the-box RTL-level Power Analysis that is within 15% of signoff.
PowerPro’s tight integration with Veloce Emulation platform provides the most comprehensive and sophisticated approach to system level power analysis under real world use case scenarios as well as in offline mode.
PowerPro utilizes Siemens EDA’s Visualizer Debug Environment that offers powerful features for visualization. PowerPro also offers powerleaks flow where redundant toggles are marked on the waveform. RTL designers can root-cause the source of redundant toggles and fix them easily by cross-probing the waveform to RTL or Schematic.
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