PowerPro is the leading power optimization technology in the industry today. With its deep sequential analysis engines, PowerPro’s optimization is able to find maximum power saving opportunities having minimal overhead in terms of area and timing.
PowerPro considerably eases the effort required by RTL designers to factor in the changes into their RTL by providing all the information needed to find and fix power issues. PowerPro’s guided power optimization allows the user to uncover power issues from early RTL stage without vectors until RTL signoff stage with power qualified vectors. This is enabled through a portfolio of multi-pronged optimization techniques applicable to different RTL stages.
During the early stage of RTL when functional vectors are available, PowerPro’s micro-architectural and combinational redundancies help users identify, quantify and fix power bugs. PowerPro’s functional analysis engine finds redundant toggles in the design that can lead to wasted power and suggests fixes to gate the source of such redundant toggles or restructure the logic to avoid wasted toggles.
With mature RTL and power qualified vectors, PowerPro’s flagship deep sequential analysis engine performs multi-cycle analysis to find chains of registers that can be gated using a common enable condition. PowerPro finds new enable conditions to clock gate registers and also strengthens existing enable conditions to result in higher power savings. The same concepts are also applied to memories and data operators.
PowerPro’s early design checks are use-case independent checks based on static analysis of the RTL that can be performed very early in the design cycle. By performing power lint on the RTL, low-hanging issues can be caught and fixed upfront. Early design checks include coverage checks that determine how much of the design registers, memories, macros, data operators etc are gated. Integrated Clock Gating or ICG checks allow RTL designer to assess if the existing ICG cells in the design are redundant from a structural or functional standpoint. Additionally, connectivity checks helps users remove unwanted logic that may be floating or unused.
Early design checks run extremely quickly and can be used to develop low-power coding guidelines for design teams. They can easily be extended to regressions and can be helpful in uncovering potential negative impact RTL changes may have on power upfront.
Micro-architectural and combinational redundancies are vector dependent checks based on functional analysis of the design. These checks can be used to perform power audit for the design and explore ways to reduce power. PowerPro performs functional analysis to find redundant toggles in the design that do not contribute to functionality and hence waste power.
Micro-architectural redundancies perform structural analysis to uncover logic structures that are not power efficient and combines that with functional analysis to quantify wasted toggles and power on account of those inefficiencies. It provides suggestions to RTL designer on how to restructure the logic in order to reduce or eliminate redundant toggles and save power.
Combinational redundancies perform functional analysis to find wasted toggles around structures like multiplexers, registers, memories, busses and data operators. Users can root-cause the source of redundant toggles and eliminate them to reduce power. Detailed reports with impact on clock gating efficiency and power are generated. GUI can be used to root-cause and fix the power issues.
PowerPro’s sequential optimization is based on Siemens EDA’s patented deep sequential analysis engine that performs multi-cycle analysis for registers and memories to find the most optimal enable conditions for clock gating and memory gating. Deep sequential analysis is a combination of an observability analysis engine and a stability analysis engine. The observability analysis engine performs deep sequential analysis on logic whose output is not observable. Stability-based analysis, however, performs deep sequential analysis on logic whose output is stable. Deep sequential analysis traverses multiple cycles to find enable condition that can be applied to gate multiple registers and shut-off the datapath logic driven by those registers, yielding significant gains.
PowerPro’s sequential optimization techniques include clock gating and memory gating. Complete information for each enable condition is provided including the memory or chain of registers it will gate along with its source reference, the exact enable expression that needs to be implemented by RTL designer, its impact in terms of clock gating efficiency improvement, power reduction, area penalty and details on the signals participating in the enable condition like their logic depth, hierarchical depth, number of signals etc.
Learn how to use PowerPro for power analysis/estimation at both RTL and gate-level and how to optimize power during RTL development for the lowest possible design power.
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