PowerPro’s sequential optimization is based on Siemens EDA’s patented deep sequential analysis engine that performs multi-cycle analysis for registers and memories to find the most optimal enable conditions for clock gating and memory gating. Deep sequential analysis is a combination of an observability analysis engine and a stability analysis engine. The observability analysis engine performs deep sequential analysis on logic whose output is not observable. Stability-based analysis, however, performs deep sequential analysis on logic whose output is stable. Deep sequential analysis traverses multiple cycles to find enable condition that can be applied to gate multiple registers and shut-off the datapath logic driven by those registers, yielding significant gains.
PowerPro’s sequential optimization techniques include clock gating and memory gating. Complete information for each enable condition is provided including the memory or chain of registers it will gate along with its source reference, the exact enable expression that needs to be implemented by RTL designer, its impact in terms of clock gating efficiency improvement, power reduction, area penalty and details on the signals participating in the enable condition like their logic depth, hierarchical depth, number of signals etc.