PowerPro Emulation driven SoC Power Analysis

PowerPro provides a comprehensive SOC power analysis solution in combination with Veloce emulation. Full chip power analysis requires scalability in terms of capacity and performance due to the size of designs and magnitude of real-world workloads.

Detailed Power Analysis

PowerPro offers all that users need to enable detailed power analysis for full chip like early power profiling with Veloce PowerApp to find windows of interest, power analysis for mixed RTL/Gate designs and UPF-aware power analysis.

Large Designs Made Easy

The biggest challenge to SoC power lies in the enormity of design sizes and the extensive trace lengths of real workloads. PowerPro has the unique ability to partition an RTL or Gate design into multiple smaller partitions and then compute power independently for each of the partitions and combine the results to provide an aggregated view of full chip power, enabling power analysis for billions of gates SoCs. With its sophisticated and robust multicore technology, PowerPro is also able to handle emulation workloads that can be run for hundreds of millions of cycles.

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Design Partitioning

SoC design sizes today can easily exceed a billion gates. Full chip power analysis is not possible with existing solutions that rely upon traditional methods of power analysis. PowerPro enables power analysis for ultra large SoCs through its unique design partitioning flow that partitions the SoC into multiple smaller blocks either automatically or through user-assistance and then computes power independently for each partition while managing all setup and inputs to deliver combined chip-level power reports.

Automatic Design Partitioning
In automatic design partitioning flow, PowerPro performs a quick reading of the design and then proposes a partition strategy to optimize resource requirements and time-to-power. PowerPro’s resource manager automatically takes care of managing partitions, constraints, design compilation, switching activity propagation and power computation without the need for any user intervention, delivering power reports for full chip.

Assisted Design Partitioning
In assisted design partitioning flow, user defines the partitions based on their bottom-up implementation. PowerPro takes the user input and then automatically takes care of managing partitions, constraints, design compilation, switching activity propagation and power computation without the need for any further user intervention, delivering power reports for full chip.

Scalable Multicore Architecture

PowerPro’s strength lies in its scalable multicore architecture that allows parallel execution of jobs in a distributed computing environment involving both local and remote machines. All parallel jobs created by PowerPro’s distributed computing framework require a low-memory footprint that allows users to allocate a large number of CPUs, scaling performance massively. Depending on the trace length of the workload, users can predictably determine and allocate the optimal number of CPUs for power computation and achieve power analysis for extremely long traces in a short turnaround time.

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PowerPro on-demand training

Learn how to use PowerPro for power analysis/estimation at both RTL and gate-level and how to optimize power during RTL development for the lowest possible design power.

PowerPro support

Access detailed documentation, releases, resources and more.

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