SoC design sizes today can easily exceed a billion gates. Full chip power analysis is not possible with existing solutions that rely upon traditional methods of power analysis. PowerPro enables power analysis for ultra large SoCs through its unique design partitioning flow that partitions the SoC into multiple smaller blocks either automatically or through user-assistance and then computes power independently for each partition while managing all setup and inputs to deliver combined chip-level power reports.
Automatic Design Partitioning
In automatic design partitioning flow, PowerPro performs a quick reading of the design and then proposes a partition strategy to optimize resource requirements and time-to-power. PowerPro’s resource manager automatically takes care of managing partitions, constraints, design compilation, switching activity propagation and power computation without the need for any user intervention, delivering power reports for full chip.
Assisted Design Partitioning
In assisted design partitioning flow, user defines the partitions based on their bottom-up implementation. PowerPro takes the user input and then automatically takes care of managing partitions, constraints, design compilation, switching activity propagation and power computation without the need for any further user intervention, delivering power reports for full chip.
