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PowerPro Automatic Power Optimization

Complex functionality and high performance being the primary challenges for RTL designers, power can come as a last-minute surprise if not paid attention to. With tight schedules for tape-out, an automatic power optimization solution can come as a life saver for design teams.

KEY FEATURES

Automatic Power Optimization

  • Fully automatic, push-button low-power RTL generation
  • Ability to configure automatic RTL generation style for PowerPro generated enable logic
  • User’s original RTL, indentation and spacing untouched and preserved
  • ECO flow to invalidate affected clock gates or memory gates

Truly Automated Optimization

PowerPro’s automatic optimization is the only truly capable, production proven automatic low-power RTL optimization solution available in the market today. Based on deep sequential analysis engines, it can find the most effective clock gating and memory gating enables to optimize power significantly and then automatically write out power optimized RTL. It also generates a script to setup SLEC-Pro which is a sequential logic equivalence checking solution and automatically runs formal verification to compare users original RTL with PowerPro’s automatically generated low-power RTL, cutting down verification effort for low-power changes significantly and resulting in multifold productivity improvements for RTL design teams.

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Sequential Optimization

PowerPro’s sequential optimization is based on Siemens EDA’s patented deep sequential analysis engine that performs multi-cycle analysis for registers and memories to find the most optimal enable conditions for clock gating and memory gating. Deep sequential analysis is a combination of an observability analysis engine and a stability analysis engine. The observability analysis engine performs deep sequential analysis on logic whose output is not observable. Stability-based analysis, however, performs deep sequential analysis on logic whose output is stable. Deep sequential analysis traverses multiple cycles to find enable condition that can be applied to gate multiple registers and shut-off the datapath logic driven by those registers, yielding significant gains.

Write RTL Engine

PowerPro’s state-of-the-art, production proven RTL writing engine automatically writes out power optimized RTL for its sequential optimization techniques, clock gating and memory gating. It inserts enable conditions into the “if” branch of the always block and adds comments to the user RTL so that PowerPro inserted enables can be easily identified. It also maintains full readability of the RTL by keeping indentation of the code and the untouched original RTL “as is”. Enable logic implemented automatically is stored in separate modules and the new file list with automatically generated RTL is available in the work directory. The Write RTL engine can be configured to write power-optimized RTL in many ways by configuring its options. Users can also select opportunities that they wish the tool to automatically implement.

SLEC-Pro Formal Verification

SLEC-Pro is a sequential logic equivalence checking tool that is shipped with PowerPro’s automatic optimization solution. SLEC-Pro is able to verify the logic equivalence between users original RTL and PowerPro’s automatically generated low-power RTL. As PowerPro find optimization opportunities that re multi-cycle in nature, a sequential LEC tool is required for its verification. User is not required to setup SLEC-Pro. PowerPro automatically generates a script with all required setup that can simply be executed to run SLEC-Pro and perform formal verification. There is no need for RTL designer to invest in formal verification of automatically optimized low-power RTL.

ECO Flow for Power Optimized RTL

Sometimes, changes may be required to a stable design that has already been synthesized and implemented. In that case, some of the enable conditions inserted by PowerPro’s automatic power optimization may become invalid. PowerPro offer an ECO flow that validates the automatically implemented gating on an ECOed design to avoid resynthesizing a stable design that has already undergone place and route. PowerPro provides eco directives to disable invalid enables in the gate-level netlist. New RTL can also be automatically generated out of PowerPro’s ECO flow to enable RTL to Gate equivalence checking after ECO is done.

PowerPro ECO Flow
RTL power optimization is a critical step in our high-performance, low-power design methodology for PC graphics, visual computing, and applications processors.
Dan Smith, Director, Hardware Engineering, NVIDIA Corporation

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