How do you get excellent quality-of-results at a competitive runtime? The challenges of design implementation at advanced process nodes require a new place-and-route paradigm.
Managing design complexity, performance/power/area targets, and time-to-market are crucial challenges in modern SoC design. Design rule complexity and meeting timing make design closure more challenging than ever, and calls for a paradigm shift in place-and-route.
Extensive use of multiple-patterning technology, EUV lithography and mixed-height cells complicates placement and routing. Fundamental changes to place-and-route technology are required to effectively achieve DRC closure.
The market wants ICs with the lowest power use and highest performance. Break-through optimization technologies can minimize power while achieving timing and area targets and controlling development cost.
Accurate post-route timing estimation is harder than ever with the increase in wire/via resistance. Avoid iterations, improve PPA, and reduce time to closure by pulling detailed route visibility earlier in the flow.
The Aprisa place-and-route platform is a detailed route-centric solution to the challenges of modern digital IC implementation.