Taking Catapult to the next level by partnering with advanced RTL Synthesis technologies such as Synopsys DC-NXT, plus Siemens EDA’s Oasys and Precision FPGA Synthesis. Catapult delivers improved QoR for Performance, Power and Area with latest process technologies.
As geometries decrease, estimation and interpolation of RTL operator synthesis for advanced FPGAs or ASIC multiVT effects becomes harder. To build optimal RTL, HLS must neither over-pipeline, nor under-pipeline the output RTL in order to tune the Performance, Power and Area results downstream.
On The Fly Characterization uses downstream physically aware synthesis tools to build a complete area/performance tradeoff of every operator needed in your design. Advanced caching across multiple users and designs reduces iterative runtime, while providing superior results for modern geometries. MultiVT option choices round out the optimization trade-offs.
MultiVT libraries deliver a wide range of power and performance. High performance gate level implementations come at a cost of power and area. Designers need a mechanism to drive VT usage to achieve the optimum tradeoff for their specific needs. Catapult delivers a multiVT approach for On-The-Fly Characterization with modern process technologies.
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The Catapult High-Level Synthesis (HLS) On-Demand training library contains a set of learning paths with modules to introduce Engineers to HLS and High-Level Verification.
A group to discuss the finer points of Design and Verification using Siemens EDA's HLS & HLV tools. Join the discussion on new topics, features, content, and technical experts.
A free and open set of libraries implemented in standard C++ for bit-accurate hardware and software design. It's an open community for exchange of knowledge and IP for HLS that can be used to accelerate both research and design.
Blog covering next generation High-Level Synthesis (HLS) design and verification methodologies and techniques.
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