Catapult Physical Aware
Taking Catapult to the next level by partnering with advanced RTL Synthesis technologies such as Synopsys DC-NXT, plus Siemens EDA’s Oasys and Precision FPGA Synthesis. Catapult delivers improved QoR for Performance, Power and Area with latest process technologies.
A Closer Connection To Physical RTL Synthesis
As geometries decrease, estimation and interpolation of RTL operator synthesis for advanced FPGAs or ASIC multiVT effects becomes harder. To build optimal RTL, HLS must neither over-pipeline, nor under-pipeline the output RTL in order to tune the Performance, Power and Area results downstream.
Getting An Exact Answer For Every Operator
On The Fly Characterization uses downstream physically aware synthesis tools to build a complete area/performance tradeoff of every operator needed in your design. Advanced caching across multiple users and designs reduces iterative runtime, while providing superior results for modern geometries. MultiVT option choices round out the optimization trade-offs.
Trading Power, Performance & Area
MultiVT libraries deliver a wide range of power and performance. High performance gate level implementations come at a cost of power and area. Designers need a mechanism to drive VT usage to achieve the optimum tradeoff for their specific needs. Catapult delivers a multiVT approach for On-The-Fly Characterization with modern process technologies.
HLS Design & Verification Blog
Blog covering next generation High-Level Synthesis (HLS) design and verification methodologies and techniques.
Catapult On-Demand Training
The Catapult High-Level Synthesis (HLS) On-Demand training library contains a set of learning paths with modules to introduce Engineers to HLS and High-Level Verification.
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