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Overview

Calibre PERC

The Calibre PERC platform is the industry leader for reliability verification solutions, enabling a vast range of IC circuit reliability checks that are not possible with traditional physical verification tools.

Get in touch with our technical team: 1-800-547-3000

Fast, accurate, automated context-aware checking in all phases of IC design verification

Automated context-aware checking has become an essential best practice for providing reliable and timely IC chips to the market. Designers can leverage the actionable net/device debug information in error results to more quickly and easily adjust layouts based on both the electrical and geometrical features in an IC design, improving both verification precision and debugging efficiency. Physical, circuit, electrical, and reliability IC design verification can all take advantage of context-aware checks to improve the quality and accuracy of results, while reducing turnaround time.

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Beyond geometry checks: Context-aware design verification
Key Features

Comprehensive reliability verification

The Calibre PERC reliability platform automatically combines netlist and layout information to perform targeted electrical checks that consider the context of the design intent for both layout-related and circuit-dependent checks.

Providing a Solid Foundation

Foundry Rule Decks

Understanding the foundry view of reliability on your design is necessary for a comprehensive reliability verification strategy. Foundry qualified and supported rule decks are essential to establishing this reliability baseline, not only to guide improvements, but also to establish best practices with internal and 3rd party IP through full-chip sign-off.

Row of marble columns | Foundry qualified and supported Calibre PERC rule decks are essential to establishing a reliability baseline, not only to guide improvements, but also to establish best practices with internal and 3rd party IP through full-chip sign-off.
Are you protected?

Electrostatic Discharge Solutions

When verifying the robustness of your electrostatic discharge (ESD) protection strategy in your design, it is essential to ensure sufficiently-sized devices and interconnect are where they need to be. Understanding the performance of these critical design elements requires a combination of topology, layout and interconnect robustness capabilities in a context-aware environment.

Electrical burst of energy | Calibre PERC provides a combination of topology, layout and interconnect robustness capabilities in a context-aware environment to help designers understand the performance of critical design elements.
Find Your Way. Where to Start?

Context-Aware Verification

Target verification rules with precision by leveraging rule deck defined circuit structures in the schematic or layout. Being able to identify the absence of required circuit elements, such as protection devices or level-shifters, is of equal importance. Find your way through the unique complexities of each design with context-aware verification.

Staircase in the woods leading to light | Calibre PERC helps designers target verification rules with precision by leveraging rule deck defined circuit structures in the schematic or layout.

Calibre PERC Featured Resources

Explore our featured resources or visit the full Calibre PERC resource library to view on-demand webinars, white papers, and fact sheets.

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Design with Calibre blog

Across all process nodes and design styles, the Calibre toolsuite delivers accurate, efficient, comprehensive IC verification and optimization, while minimizing resource usage and tapeout schedules.

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