Calibre PERC & 3DPERC

IC design and verification teams, from initial IP circuit designers, to full-chip layout design verification. Use of Calibre PERC is extensive throughout the IC design flow & verification flows. Early schematic verification ensures the structures being designed are not missing any critical elements, and those that are there, are correctly sized. During layout, Calibre PERC is used to validate that the physical implementation of these designs are robust and meet critical design robustness & reliability expectations.

The focus of Calibre PERC is enabling a vast range of IC circuit reliability checks that are not possible with traditional physical verification tools. It is the industry leader for electrostatic discharge (ESD) and latch-up checks and has the unique capability to recognize user defined circuit structures in the schematic or layout and to apply precise design rules that apply for these circuits. It can also flag the absence of circuit elements, such as ESD protection devices or level-shifters, that are required at certain locations in the schematic or layout.

The full range of the design flow is supported, from early netlist creation through to final layout sign-off verification.

Running Calibre PERC for most designers is often as simple as getting access to the foundry provided rule deck for the process node that you are using. Typically CAD teams make these rule decks available for the designers/product teams to use. Foundry rule decks may include a number of flows. These are typically focused on ESD and EOS and may include point-to-point resistance, current density, latch-up and voltage-aware DRC flows.

Yes, Calibre PERC makes extensive use of AI/ML capabilities when it comes to ensuring jobs are run efficiently in our interconnect robustness flows. These flows have internal optimizations driven by AI/ML that simplify the user experience and increase productivity. For more information on Calibre AI/ML products visit our Calibre Intelligence page.

Foundry provided sign-off rule decks create a baseline for reliability verification on your design. As Foundries need to support a broad spectrum of customer design reliability needs for each process node, they may not be optimized for the mission profile of your design. Calibre PERC provides a capability to deliver SPICE-accurate transient simulation. This context-aware ESD simulation flow leverages device breakdown models and the Solido Simulation Suite.

Yes, Calibre PERC, like many of the design side Calibre tools is ISO 26262 certified. To request a copy of the certification documents, please send email to Calibre ISO26262

Access to training is through our Siemens Xcelerator Academy On-Demand Training portal.

IC design and verification teams creating 3D IC design assemblies.

The focus of the Calibre 3DPERC is to perform reliability verification on 3D IC assemblies. Many verification tasks from the standalone die runs can be elegantly leveraged in the assembly context to improve productivity.

Any IC design that has a corresponding Calibre PERC rule deck and is described in a Calibre 3DStack assembly.

Users launch Calibre 3DPERC much the same was as they launch other Calibre products. Assembly information from Calibre 3DStack is leveraged to understand how the dies go together.

To learn more about Calibre 3D IC products, visit our dedicated page for detailed information on features, solutions, and how our tools can enhance your design process. Click here to dive deeper: Calibre 3D IC.