Parasitic Extraction

Calibre xACT 3D

Calibre xACT 3D parasitic extraction delivers innovative field-solver technology for accurate results sooner. Multi-threaded and distributed processing ensures virtually unlimited design scope with fast, scalable performance comparable to rule-based extraction.

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Glowing gold cube surrounded by circuitry | Calibre xACT 3D field-solver technology delivers multi-threaded and distributed processing for fast, scalable parasitic extraction.
White paper

Advancing the Art of Parasitic Extraction with Calibre

The Calibre xACT platform, with integrated Calibre xACT 3D and Calibre xL functionality, provides designers with a fast, highly accurate, and multi-purpose parasitic extraction tool that enables post-layout simulation across a wide range of designs and advanced process nodes. With attofarad accuracy, high performance, and advanced device modeling, the Calibre xACT solution gives designers confidence that their chip will meet or exceed performance expectations.

Accurate parasitic extraction is crucial to integrated circuit design performance and reliability

Accurate parasitic extraction results are of utmost importance for designers of high-performance integrated circuits (ICs) at advanced nodes. Advanced parasitic extraction tools like the Calibre xACT platform combine field solver accuracy with table-based speed to provide fast, yet accurate parasitic extraction for all styles of IC designs, including digital application-specific integrated circuits (ASICs), system-on-chips (SoCs), analog/mixed-signal (AMS), radio frequency (RF), intellectual property (IP), cell libraries, and both digital and analog custom designs. Built-in heuristics automatically select the appropriate extraction engine and technique for back-end-of-line (BEOL) and middle-of-line (MOL) geometries, enabling engineers to get the optimum blend of accuracy and performance, regardless of design style.

With its ability to quickly and accurately manage complex devices like finFETS, complex processes like multi-patterning and non-Manhattan routing, and specialized processes such as high-frequency design extraction, TICER reduction, and broadband range sweeps, the Calibre xACT platform supports all parasitic extraction requirements in advanced process node design.

electronic images portraying Accuracy, Performance, Technology, Integrated 3D | The Calibre xACT platform, with integrated Calibre xACT 3D and Calibre xL functionality, provides designers with a fast, highly accurate, and multi-purpose parasitic extraction tool that enables post-layout simulation across a wide range of designs and advanced process nodes.
Key Features

Next-Generation Fast Field Solver Parasitic Extraction

The Calibre xACT 3D field solver extracts complex context-sensitive device and interconnect parasitic effects needed to accurately predict circuit behavior. Innovative functionality accelerates performance compared with traditional field solvers, but without compromising accuracy.


Calibre xACT 3D frequently asked questions

What is a field solver?

In the world of electrical engineering, a field solver is electromagnetic simulation software for accurately predicting and analyzing the behavior of electric fields and electromagnetic waves on an integrated circuit. Rather than relying on simplified models or theoretical calculations, a field solver uses advanced numerical methods to simulate 3D interactions between electric charges, currents, and materials.

3D view of an inverter as seen by Calibre xACT 3D

xACTView helps visualize the Calibre xACT 3D design in 3D format

What is parasitic extraction?

Parasitic extraction is the process of computing the capacitance, resistance, and inductance of metal interconnect wires in a semiconductor device. These parasitic effects arise due to the non-ideal behavior of wires, transistors, and other components, and can significantly impact the performance and reliability of a chip.

How do you use EM solvers for parasitic extraction?

Some electromagnetic (EM) solvers work well with chip design to have a more accurate parasitic extraction. The EM solver integrates with a layout vs schematic (LVS) tool, so that the device parameters are calculated by LVS, and the parasitics are measured with a field solver.

Why is parasitic extraction important in IC design?

As integrated circuits (ICs) become more complex, designers face increasing challenges in ensuring accurate and reliable operation. One critical aspect of this is parasitic extraction, the process of determining the effects of physical structures such as wires, transistors, and capacitors on circuit performance. Without accurate parasitic extraction, designers risk poor performance, increased power consumption, and even catastrophic failure. By accounting for parasitic effects during the design process, engineers can optimize circuit performance and minimize the risk of costly errors. Parasitic extraction is an essential tool in modern IC design, enabling engineers to create chips that operate efficiently and reliably in a wide range of applications.

What elements are in parasitic extraction?

Some of the commonly extracted parasitic elements include resistors (R), inductors (L), and capacitors (C). These elements arise from the inherent properties of the materials used in building electronic devices and circuits.

How do parasitic elements affect performance of the chip?

Capacitance can cause unwanted coupling between different parts of the circuit and reduce high-frequency performance. Inductance can cause signal delay and reduce high-frequency performance, while resistance can lead to power losses, voltage drops, and thermal problems. These effects can reduce power efficiency, crosstalk, and signal-to-noise ratio, and lead to malfunctions, which could negatively impact chip performance.

What is parasitic capacitance?

Parasitic capacitance refers to the capacitance that unintentionally exists between two conductors. This capacitance is a function of proximity of the conductors, their surface area, and the dielectric constant between them. The impact of parasitic capacitance can be significant, leading to distortion in electronic signals and slowing down the performance of circuits. Because it is often difficult to eliminate this capacitance entirely, engineers must find ways to mitigate its effects through careful design and layout considerations.

Capacitance is a function of the common area between metal 1 (M1) and metal 2 (M2), and the equivalent dielectric constant of all the dielectric layers in between them.

What is parasitic resistance?

Parasitic resistance occurs when there is unwanted resistance present in the circuit due to the connections, components, or layout of the circuit. Parasitic resistance depends on the type of metal, and the width and thickness of the metal interconnect.

What is parasitic inductance?

Inductance is a fundamental property of an electrical circuit, and it is the measure of an object's ability to generate an electromotive force (EMF) in response to a change in the electrical current flowing through it. The physical unit for measuring inductance is the henry. Essentially, inductance describes how much a circuit opposes changes in the electrical current flowing through it. The more inductance a circuit has, the more it will resist.

When calculating parasitic inductance with Calibre xL, a bundle is formed of the signal wires, along with the power and ground wires, and the DC resistor is converted to a frequency dependent resistor and an inductor.

“Calibre xL” Calibre xL Extraction | Siemens Software calculates parasitic inductance, and is integrated with Calibre xACT, Calibre xACT 3D and Calibre xRC to provide a unified RLC netlist.

What is a full wave solver?

Full wave analysis is an approach to solving the complete set of Maxwells equations without any simplifying assumptions. The fields described by these equations are typically time-variant and frequency-dependent, making them a challenge to accurately analyze. Full wave solvers are typically used for structures such as antennas and transmission lines operating at a high frequency.

Is Calibre xACT 3D a full wave solver?

No, Calibre xACT 3D is not a full wave solver. It is a capacitance field solver. Unlike a full wave solver which has very low capacity, Calibre xACT 3D can be run on a full chip. It is integrated with Calibre xL to provide inductance, and Calibre xACT to provide resistance. It is typically used to calculate parasitics for an analog, RF, or digital integrated circuit.

Can you run Calibre xACT 3D on a full chip?

Yes, you can run Calibre xACT 3D on a full chip. One example is for a 12nm memory with 513,000 nets, Calibre xACT 3D in RCC mode took 2.1 hours to run on 16 CPUs.

What are the requirements to running Calibre xACT 3D?

To run Calibre xACT 3D, you need a Calibre xACT 3D license, the design schematic and layout, and a Calibre xRC or Calibre xACT rule deck downloaded from the foundry web site.

Is Calibre xACT 3D integrated into Virtuoso?

Yes, Calibre xACT 3D is integrated into Virtuoso. Starting the run uses Calibre Interactive GUI, and debugging the parasitics is done with Calibre RVE, which allows parasitics to be highlighted on the layout. The parasitic output is in Calibre view format, which is a graphical extracted view.

Calibre RVE parasitic browser showing parasitic values sorted by value

Can you do reduction with Calibre xACT 3D?

Yes, Calibre xACT 3D has many reduction algorithms built in, including frequency-based reduction, threshold-based reduction, via reduction, and metal fill reduction.

Via Reduction in Calibre xACT 3D, keeping the perimeter vias in each cluster, while dropping internal ones

Calibre xACT 3D Featured Resources

Explore our featured resources or visit the full Calibre xACT 3D resource library to view on-demand webinars, white papers, and fact sheets.

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