Increasing operating frequencies for analog/RF designs mean interconnect inductance parasitic extraction is now required to ensure accurate circuit performance and high reliability. Automated field solver-based inductance extraction of both self and mutual parasitics enables IC companies to deliver analog/RF chips that provide the intended level of performance and reliability.
![The Calibre RealTime Custom interface enables custom/AMS layout designers to access Calibre signoff DRC in the design flow, using full foundry-qualified Calibre rule decks and analysis engines.](https://images.sw.cdn.siemens.com/siemens-disw-assets/public/6s8fYhH7JpqaysRwxeMdp6/en-US/calrtc-comparison-2-640x360.jpg?auto=format,compress&w=843&q=60)