With increasing operating frequencies, interconnect lines exhibit inductive effects, with significant impact on chip behavior and performance. Parasitic on-chip inductance extraction is crucial for accurate simulation and timely tape-out of high-frequency RF, mixed signal and custom digital designs.
Full-chip, high-performance, parasitic self-inductance extraction. Accurate extraction of frequency-dependent loop inductance and resistance. Efficient, realizable model order (RLC) reduction. Return-path selection and net-based extraction frequency selection.
Fully integrated with Calibre LVS, xACT, and xRC tools. Enables accurate analysis of high frequency effects in nanometer technology. Provides manageable netlists and mixed-level outputs for easy re-simulation without loss of accuracy. Provides highly correlated field solver and silicon-tested accuracy for on analog, RF and custom digital nanometer designs.
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Across all process nodes and design styles, the Calibre toolsuite delivers accurate, efficient, comprehensive IC verification and optimization, while minimizing resource usage and tapeout schedules.