With its integrated fast 3D field solver and highly parallel architecture, the Calibre xACT parasitic extraction tool combines accuracy with the performance needed for multi-million instance designs.
Get in touch with our technical team: 1-800-547-3000
The Calibre xACT solution offers parasitic extraction options for interconnect modeling that ensure accurate capture of parasitic and layout-dependent effects for non-planar devices in advanced node designs, simultaneous multi-corner extraction for efficient processing, and accurate identification of EM current density violations, as well as accurate extraction and modeling for 3D IC package designs.
Versatile parasitic extraction platform provides accurate, deterministic, repeatable results with 10x the performance of previous solutions to handle a wide range of designs and advanced processes
Supports the most advanced foundry device models, including FinFET, and leading edge process nodes with accurate, deterministic results. Results from simultaneous multi-corner extraction precisely match single-corner results.
Efficient algorithms, advanced computational methods, and a multi-threaded, distributed processing architecture provide performance and capacity to handle multi-million instance digital designs.
Uses standard SVRF rule files to produce parasitic netlist formats. Part of the Calibre platform and supported by all major foundries. Provides trusted device recognition, connectivity extraction and ease-of-use.
Parasitic extraction is the process of computing the capacitance, resistance, and inductance of metal interconnect wires in a semiconductor device. These parasitic effects arise due to the non-ideal behavior of wires, transistors, and other components, and can significantly impact the performance and reliability of a chip.
As integrated circuits (ICs) become more complex, designers face increasing challenges in ensuring accurate and reliable operation. One critical aspect of this is parasitic extraction, the process of determining the effects of physical structures such as wires, transistors, and capacitors on circuit performance. Without accurate parasitic extraction, designers risk poor performance, increased power consumption, and even catastrophic failure. By accounting for parasitic effects during the design process, engineers can optimize circuit performance and minimize the risk of costly errors. Parasitic extraction is an essential tool in modern IC design, enabling engineers to create chips that operate efficiently and reliably in a wide range of applications.
A rule-based engine has pre-defined models to extract the parasitic components, It measures distances between polygons and uses table look up, which enables fast performance for large macros all the way to complete designs.
In the world of electrical engineering, a field solver is electromagnetic simulation software for accurately predicting and analyzing the behavior of electric fields and electromagnetic waves on an integrated circuit. Rather than relying on simplified models or theoretical calculations, a field solver uses advanced numerical methods to simulate 3D interactions between electric charges, currents, and materials.
Calibre xACT uses a hybrid approach which uses the field solver around the devices and on the lower metal layers, and a table-based engine for the upper metal layers. The table-based methodology measures distances between polygons and uses look up tables, which enables fast performance. The field solver models the 3D effects around devices with the highest possible accuracy, this hybrid approach is the best combination of performance and accuracy for advanced nanometer processes.
Calibre xRC is a rule-based tool that performs parasitic extraction for mature nodes, 20nm and above.
Calibre xACT is a rule-based tool, paired with Calibre xACT3d field solver for advanced nodes, 16nm or below.
Yes, Calibre xACT supports both the analog and digital flows. Calibre xACT can be used for digital flows on all nodes.
To run Calibre xACT on analog designs, you need a Calibre xACT license; a layout database in GDSII or OASIS format with defined connectivity; a source netlist if you require schematic names in the parasitic Netlist; and a Calibre xACT rule deck downloaded from the foundry website.
To run Calibre xACT for the digital flow, you need a Calibre xACT license; design DEF file(s) with defined connectivity; a technology LEF file, all other LEF files such as cell libraries, IP blocks, and via definitions; a Calibre xACT or Calibre xRC rule deck downloaded from the foundry website.
Yes, “Calibre xL” Calibre xL Extraction | Siemens Software calculates parasitic inductance, and is integrated with Calibre xACT, Calibre xACT 3D and Calibre xRC to provide a unified RLC netlist.
Yes, Calibre xACT is integrated into Virtuoso. The tool is invoked in the Calibre Interactive GUI, and debugging the parasitics is done with Calibre RVE, which allows parasitics to be highlighted on the layout. The parasitic output is in Calibre-view format, which is a graphical extracted view.
Yes, Calibre xACT has many reduction algorithms built in, including frequency-based reduction, threshold-based reduction, via reduction, and metal fill reduction.
Yes, Calibre xACT supports multi-corner extraction, in which all or a selection of interconnect, multi-patterning and temperature corners can be extracted in a single run with less than 10% runtime overhead per corner.
Calibre xACT includes a selective net processing capability that designers can use to tailor the amount of data generated for simulation by selecting the specific parasitic model they want for each net. Designers can also control extraction by layer.
Calibre xACT can also generate multiple netlists from a single parasitic extraction database (extraction run).
Users can also run select net extraction, specifying which nets to extract parasitics for. Furthermore, you can specify whether to extract specific nets with fieldsolver accuracy by xACT 3D, while all other nets are extracted normally by xACT.
xACT generates all industry-standard netlist formats, suitable for most types of post-layout analysis: HSPICE, DSPF, SPEF, Calibreview. C-only netlists can be generated for noise analysis, resistance-only netlists for power analysis, RC netlists for timing, and RCC netlists for signal integrity analysis.
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Across all process nodes and design styles, the Calibre tool suite delivers accurate, efficient, comprehensive IC verification and optimization, while minimizing resource usage and tapeout schedules.