Calibre 3DStress

Thermo-mechanical stress simulation is the application of computational models to synthesize the effects of temperature and mechanical loads on the 3D IC package structure and materials, which results in stresses and deformations within the package. 

Die-level stress and warpage can induce current or add resistance at the device level. These stresses would not exist as a stand-alone SoC. With a system-in-package, it’s necessary to consider how the packaging process can affect the circuit function after packaging, so as not to cause circuit failures after packaging process stages. Furthermore, stresses can be modeled to ensure that issues during operation of the product are not influenced by die-level stress. 

Using traditional Calibre functionality, the layout of the design can be translated into structural details to compute effective material properties. These effective properties are then used in the computational model, combined with process conditions, to simulate the resulting stresses in the package, down to the die-level. 

Thermo-mechanical stress uses temperature change and mechanical material properties to compute resulting stress and warpage. Thermal analysis uses thermal material properties and power inputs to compute resulting thermal profiles. Both will use the layout and package structural components, but the material properties and computation are different. Calibre 3DThermal offers a die-level thermal analysis solution in our Calibre 3D IC suite. 

Calibre 3DStress offers a global analysis mode for coarse analysis at the package level without die-level detail. For the die in the package, simplifications can be done to represent the die, but there will not be good accuracy at the transistor level using material and structure simplifications. To maintain feature scale accuracy of stress simulation, feature level structure and material details are required.