Heterogeneous and homogeneous 2.5/3DIC Package Connectivity Planning, assembly prototyping, & system technology co-optimization
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Early exploration and prototyping allows engineers to evaluate different IC, interposer, package, and PCB integration scenarios in order to meet overall device size, performance, power, routability, and cost goals prior to detailed implementation.
Construction and visualization of system-level logical connectivity of multi-die, multi-component, and multi-substrate IC package designs. Provides the ability to use graphical schematics to derive all or partial logical connectivity along with spreadsheet or interactive creation.
Graphical display of the complete system in a single floorplan-in-floorplan view with flight lines indicating connectivity between devices. From this floor plan view, rules-based connectivity optimization can be run from any direction by signal, bus, or interface. Escape and breakout routing can be easily included to drive the optimization process.
In conjunction with Calibre 3DSTACK, Xpedition Substrate Integrator uniquely identifies geometries per layer per die placement in the assembly, allowing accurate checking between dies. With the ability to differentiate the layers of interest per individual die placement, Calibre 3DSTACK enables designers to verify the physical attributes of each die.
These tools allowed us to detect out-of-sync connectivity between the design intent and the design implementation, preventing potential opens/shorts that could have occurred between the package and the PCB. If undetected, these errors could have created a costly time-consuming respin.
"The 10-week delay to market would have been very costly to eSilicon. Having the methodology in place to catch these errors prior to tape out pretty much pays for itself. We needed a more robust methodology to avoid these manual type mistakes that were inherent in our previous process. "
Tony Mastroianni, Senior Director of Engineering
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