Questa Visualizer Debug

Overview

Questa Visualizer Debug

High performance, scalable, context-aware debug supporting the complete logic verification flow including simulation, emulation, prototyping, testbench, low-power, and assertion analysis. Intuitive and easy to use, Visualizer improves debug productivity of today's complex SoCs and FPGAs.


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Visualizer Debug image

Questa Visualizer Debug Resources

KEY FEATURES

Debug Complex, Mixed Verification Environments

Visualizer has several features that improve debug productivity for SystemVerilog/UVM, transaction-level, RTL, gate-level and low-power design and verification. It provides a full set of synchronized views for analyzing waveforms, source code, and connectivity.

RTL Debug

Wave with Transaction Coloring and Biometric Search

Class object handles from the driver in a UVM testbench. These are all the transactions that were sent from the sequencer to the driver. The Virtual interface is also shown, along with the transactions from the channel. Additionally the values displayed are colored according to the biometric searches that have been created.

Wave with transaction coloring and Biometric search with values colored according to the biometric searches that have been created.

Root cause analysis

TimeCone

The Visualizer Debug Environment allows you to find unknowns (X values), trace an event back in time to the root cause of that event through multiple clock domains and find origins of unknowns using the Time Cone window.

The Visualizer Debug Environment allows you to find unknowns such as x values.

Causality tracing

Connectivity Tracer

Automatic fan-in display using signal highlight from a signal back to the next primary input or flip flop.

visualizer Debug software showing connectivity tracer

Physical Connectivity

Logic Cone

The Logic Cone window allows you to explore the “physical” connectivity of your design, to trace signals that propagate through the design, and to identify the cause of unexpected inputs, by showing a graphic view of the RTL objects in your design.

The Logic Cone window allows you to explore the “physical” connectivity of your design, to trace signals that propagate through the design, and to identify the cause of unexpected inputs, by showing a graphic view of the RTL objects in your design.

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Verification Academy

Verification Academy provides the skills necessary to mature an organization's functional verification process capabilities, providing a methodological bridge between high-level value propositions and the low-level details.

Verification Horizons Blog

Insight and updates on concepts, values, standards, methodologies, and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them.

Verification Horizons Issue

The Verification Horizons publication provides concepts, values, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them.