Vista Virtual Prototyping

{"showBreadcrumbs":true,"breadcrumbs":[{"title":"Siemens EDA Software","path":"/en-US/"},{"title":"IC Tool Portfolio","path":"/en-US/ic"},{"title":"Vista Virtual Prototyping","path":""}],"tagline":"Electronic System Level Design","title":"Vista Flow","description":"The Vista Flow consists of the steps typically used by SoC architects, hardware engineers, and software engineers to create TLM Models, assemble and configure the system, simulate, verify and debug, analyze and optimize performance, and power and integrate with the software.","pricingCurrency":"US$","image":{"url":"https://images.sw.cdn.siemens.com/siemens-disw-assets/public/2ssyXHg7We2qzaK4nK4rWy/en-US/vista-transaction-sequence-viewer_640x480.jpg?w=640","alt":"Screenshot of Vista flow transaction sequence","linkData":"{\"name\":\"vista-flow transaction-sequence-viewer 640x480\",\"id\":\"2ssyXHg7We2qzaK4nK4rWy\",\"contentType\":\"image/jpeg\"}"},"phoneIcon":true,"moreInformation":"Get in touch with our sales team 1-800-547-3000"}
Electronic System Level Design

Vista Flow

The Vista Flow consists of the steps typically used by SoC architects, hardware engineers, and software engineers to create TLM Models, assemble and configure the system, simulate, verify and debug, analyze and optimize performance, and power and integrate with the software.


Get in touch with our sales team 1-800-547-3000

Screenshot of Vista flow transaction sequence
Key Benefits

Create TLM models, debug, optimize, and more

  • Architecture design and exploration

  • Allow hardware / software tradeoffs analysis

  • Early assessment of performance and power

  • Virtual platform for software integration and validation

  • Reference modeling for RTL verification

  • Minimizes risks and maximizes quality of results



{"items":[{"title":"Quickly explore complex micro-architecture alternatives","subtitle":"Facilitate TLM model creation","background":"pale-blue","description":"<p>Vista Model Builder automates the functionality modeling with a set of TLM classes and convenience layer for more efficient and guided behavioral modeling. A TLM code skeleton is automatically derived/generated from a set of ports, registers, and memory declarations, generating compact SystemC source code compliant with TLM 2.0, so users can then model the internal behavior only on their own.</p>","image":"https://images.sw.cdn.siemens.com/siemens-disw-assets/public/2ssyXHg7We2qzaK4nK4rWy/en-US/vista-transaction-sequence-viewer_640x480.jpg?w=640&q=60","imageAlt":"Screenshot of Vista flow transaction sequence","imageTitle":"Screenshot of Vista flow transaction sequence","rightIcon":"fal fa-long-arrow-right fa-lg","imageAlign":"image-right"},{"title":"Vista Architect Environment","subtitle":"TLM 2.0 Compliant Processors","background":"light-gray","description":"<p><b>Vista Architect </b>offers a set of fast generic models for initial platform assembly and early validation. All models are TLM 2.0 compliant and can be instantiated as building blocks through a text-based format or a block diagram format for assembling any target platform.</p>","image":"https://images.sw.cdn.siemens.com/siemens-disw-assets/public/5jjX6vv0wVAl5NbYfq7PdX/en-US/vista-flow_tlm-models_640x480.jpg?w=640&q=60","imageAlt":"Screenshoot of Vista flow TLM models ","imageTitle":"Screenshoot of Vista flow TLM models ","rightIcon":"fal fa-long-arrow-right fa-lg","imageAlign":"image-left"},{"title":"Verify and Debug the System","subtitle":"Debugging Vista Processes","background":"white","description":"<p>Vista Architect offers the industry&#39;s most advanced SystemC debug toolset (Vista Debug) designed to validate and debug SystemC TLM platforms. At the architecture level, verification is focused on validating the correct interaction among various IPs and the appropriate flow of data. Vista Architect presents an innovative debugging and tracing concept that focuses on high-level system debug and data flow analysis.</p>","image":"https://images.sw.cdn.siemens.com/siemens-disw-assets/public/6OR344XQawir0nbMe85DJL/en-US/vista-transaction-sequence-viewer_640x480.jpg?w=640&q=60","imageAlt":"Screenshot of Vista transaction sequence viewer","imageTitle":"Screenshot of Vista transaction sequence viewer","rightIcon":"fal fa-long-arrow-right fa-lg","imageAlign":"image-right"},{"title":"Assemble and Configure the System","subtitle":"Block Diagram Editor","background":"pale-blue","description":"<p>During the architecture design phase, models can be intuitively instantiated and assembled into various architecture configurations, interconnect layering, and memory hierarchies. Vista&#39;s powerful block diagram editor provides an intuitive graphical platform assembly, editing, and visualization. Vista&#39;s text editor assembling mechanism enables users to connect their platform in a text-based form.</p>","image":"https://images.sw.cdn.siemens.com/siemens-disw-assets/public/5FobzlAm4ZDXklG9S5aARj/en-US/vista-flow_assemble-and-configure_640x480.jpg?w=640&q=60","imageAlt":"Screenshot of Vista's image processing platform example","imageTitle":"Screenshot of Vista's image processing platform example","rightIcon":"fal fa-long-arrow-right fa-lg","imageAlign":"image-left"},{"title":"Integrate with Software","subtitle":"Integrated with Codebench","background":"light-gray","description":"<p>Users can test and debug the hardware that is driven by software or produce a virtual platform to run firmware, operating systems, or hardware-dependent software applications.\r</br>\r</br>Vista is integrated with Codebench Virtual Edition that provides the capability to display HW and SW traces together on one timeline to reveal how software execution affects the behavior of the hardware.</p>","image":"https://images.sw.cdn.siemens.com/siemens-disw-assets/public/16aG3n2qzRUjHN3Ro8Hwzo/en-US/vista-flow_model-builder-timing-policies_640x480.jpg?w=640&q=60","imageAlt":"Screenshot of Vista flow model builder timing policies","imageTitle":"Screenshot of Vista flow model builder timing policies","rightIcon":"fal fa-long-arrow-right fa-lg","imageAlign":"image-right"},{"title":"Quickly Change the Micro-architecture","subtitle":"Exercise Various Scenarios","background":"white","description":"<p><b>Vista Architect</b> offers a powerful analysis and reporting toolset that allows users to intuitively analyze different performance and power metrics by looking at load peaks, average latencies, throughput, and utilization on any port, bus, or sub-system without any manual instrumentation.</p>","image":"https://images.sw.cdn.siemens.com/siemens-disw-assets/public/c9BSxBzqKDYDRgDKqwbHf/en-US/vista-flow_simulation-console_640x480.jpg?w=640&q=60","imageAlt":"Screenshot of Vista flow simulation console","imageTitle":"Screenshot of Vista flow simulation console","rightIcon":"fal fa-long-arrow-right fa-lg","imageAlign":"image-left"}],"env":"master","locale":"en-US"}

Facilitate TLM model creation

Quickly explore complex micro-architecture alternatives

<p>Vista Model Builder automates the functionality modeling with a set of TLM classes and convenience layer for more efficient and guided behavioral modeling. A TLM code skeleton is automatically derived/generated from a set of ports, registers, and memory declarations, generating compact SystemC source code compliant with TLM 2.0, so users can then model the internal behavior only on their own.</p>

Screenshot of Vista flow transaction sequence

TLM 2.0 Compliant Processors

Vista Architect Environment

<p><b>Vista Architect </b>offers a set of fast generic models for initial platform assembly and early validation. All models are TLM 2.0 compliant and can be instantiated as building blocks through a text-based format or a block diagram format for assembling any target platform.</p>

Screenshoot of Vista flow TLM models

Debugging Vista Processes

Verify and Debug the System

<p>Vista Architect offers the industry&#39;s most advanced SystemC debug toolset (Vista Debug) designed to validate and debug SystemC TLM platforms. At the architecture level, verification is focused on validating the correct interaction among various IPs and the appropriate flow of data. Vista Architect presents an innovative debugging and tracing concept that focuses on high-level system debug and data flow analysis.</p>

Screenshot of Vista transaction sequence viewer

Block Diagram Editor

Assemble and Configure the System

<p>During the architecture design phase, models can be intuitively instantiated and assembled into various architecture configurations, interconnect layering, and memory hierarchies. Vista&#39;s powerful block diagram editor provides an intuitive graphical platform assembly, editing, and visualization. Vista&#39;s text editor assembling mechanism enables users to connect their platform in a text-based form.</p>

Screenshot of Vista's image processing platform example

Integrated with Codebench

Integrate with Software

<p>Users can test and debug the hardware that is driven by software or produce a virtual platform to run firmware, operating systems, or hardware-dependent software applications. </br> </br>Vista is integrated with Codebench Virtual Edition that provides the capability to display HW and SW traces together on one timeline to reveal how software execution affects the behavior of the hardware.</p>

Screenshot of Vista flow model builder timing policies

Exercise Various Scenarios

Quickly Change the Micro-architecture

<p><b>Vista Architect</b> offers a powerful analysis and reporting toolset that allows users to intuitively analyze different performance and power metrics by looking at load peaks, average latencies, throughput, and utilization on any port, bus, or sub-system without any manual instrumentation.</p>

Screenshot of Vista flow simulation console

Ready to talk to someone today?

We're standing by to answer your questions.

Email us

Get in touch with our sales team 1-800-547-3000 or 1-503-685-8000

Verification Academy

Verification Academy provides the skills necessary to mature an organization's functional verification process capabilities, providing a methodological bridge between high-level value propositions and the low-level details.

Verification Horizons Blog

Insight and updates on concepts, values, standards, methodologies, and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them.

Verification Horizons Issue

The Verification Horizons publication provides concepts, values, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them.