Verifying today’s complex SoC designs with their ever growing software, requires a new class of hardware-assisted verification platform. A highly scalable, FPGA-based enterprise prototyping system, combining fast and congruent transition from emulation with significant runtime performance gains.
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Veloce Primo CS blade-based architecture provides the flexibility to run any workload from small IP to multi-billion gate SoC designs. Common compile and runtime software ensures design bring-up is fast. Featuring AMD’s VP1902 Versal FPGAs, Veloce Primo CS improves runtime performance by 5x or more.
Veloce Primo CS shares the same compile software with Veloce Strato CS. Not only does this provide full congruency between the platforms, it also enables fast migration of a design from emulation to prototyping, often in days instead of months. Veloce Primo CS also shares runtime software with Veloce Strato CS, so the user stays in the same environment on both platforms, boosting usability and productivity.
Veloce Primo CS will typically run the same design about 5 times faster than Veloce Strato CS, enabling full OS boot and completing workloads in less time. This makes it the ideal platform for early software validation and hardware/software integration. Due to its innovative hardware architecture this high performance scales with capacity, no matter how big the design you will always see a performance gain.
Veloce Primo CS features a blade-based architecture, providing flexibility and scalability, to assemble systems that match the Veloce Strato CS capacity of +40B gates. The single-FPGA granularity and multi-user capabilities allows heterogenous workloads to run efficiently and without loss of capacity. Each Veloce Primo CS blade can accommodate up to 8 concurrent users, that’s up to 128 users per full tower.
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