U2U24 - CICV Track Sessions

The Custom IC Verification Track had a great lineup of customer presented sessions at U2U 2024! If you missed the live event, you can now enjoy featured track recordings from AWS, Microsoft, SiTime, NVIDIA and Allegro.

Featured On-Demand Resources

U2U - Custom IC Verification Track User Presentations

PowerPoint slide that states User2User, Accelerating PMIC Verification Using AI-powered Solido Design Environment and Analog FastSPICE. Rajiv Damodaran Prabha, Ravi Shankar Gaddam, Meghana Gulien Raghuram. Allegro Microsystems.

User2User NA 2024 SESSION

Allegro AI accelerated PMIC verification

Learn how Allegro MicroSystems leveraged AI-powered Solido Design Environment and Analog FastSPICE to accelerate PMIC verification, resulting in an overall 5X reduction in verification time.

PowerPoint slide that states User2User, How AWS cloud compute helps scale custome IC verification workloads, Azim Siddiqu, Senior Solutions Architect, AWS, Wei Lii Tan, Director of Product Management, Siemens EDA.

User2User NA 2024 SESSION

Scale custom IC verification workloads with AWS

Watch this session and learn how to leverage AWS cloud capacity for full cloud migration or peak demand expansion for custom IC verification workloads, and achieve faster time-to-market.

PowerPoint slide that states User2User, Microsoft Focus on IPQA with Solido IP Validation, Martin Sanchex, Principal Silicon IP Quality Lead - Microsoft

User2User NA 2024 SESSION

Microsoft IP QA with Solido IP Validation

Learn how Microsoft leverages Solido IP Validation to address IP quality issues early in the design process, saving time and money on potential (ECOs), improving overall IP quality in production and integration flows.

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PowerPoint slide that states User2User, Accelerating verification of high preciscion MEMS based oscillators SoC with AFS XT and Symphony, Vikram Vagapally, Principal CAD Engineer. SiTime Corporation, CA.

User2User NA 2024 SESSION

SiTime verification acceleration with AFS

Learn how SiTime leverages AFS, Symphony and Solido Design Environment to ensure seamless integration between the analog and digital components and accelerate verification of high precision MEMS based oscillators SoC.

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PowerPoint slide that states User2User, Utilizing Solido Additive Learning Technology to Speed Up Standard Cell Library Verification, Chengcheng Liu, Hardware Engineering Manager at NVIDIA.

User2User NA 2024 SESSION

NVIDA AI accelerated library verification

Learn how NVIDIA leveraged Solido Additive Learning technology to speedup standard cell library verification with Solido Design Environment while maintaining the same accuracy on verifying a new PDK revision.

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User2User EU 2024 SESSION

Proactive IP Validation with Solido Crosscheck at ST

Learn how ST leverages Solido Crosscheck within their IP QA infrastructure to manage IP complexity, providing a comprehensive, proactive IP Validation solution to improve quality of silicon and accelerate SoC delivery.

User2User EU 2024 SESSION

Symphony enablement in ST's SmartPower Technologies

Learn how ST leveraged Symphony and Visualizer to enhance verification throughput for SmartPower Technologies and analyze and debug the interface between analog and digital in an easier and faster way.

User2User EU 2024 SESSION

Using Solido to evaluate stdcell libs at Infineon

Learn how Solido Library Profiler and Generator enable users at Infineon to compare and profile .libs coming from different IP sources so optimal dataset can be chosen, leading to better PPA analysis and shorter design cycles.

User2User EU 2024 SESSION

Leveraging Solido Additive Learning for NVM at ST

Learn how ST uses Solido PVTMC Verifier to predict the dispersion of analog parameters over PVT, and Solido Additive Learning to re-use previous results, reducing the number of runs and accelerating the verification phase.

User2User EU 2024 SESSION

Silicon Creations 3nm PLL Design and Simulaiton

Learn how Silicon Creations harnesses Siemens SPICE technology to manage constant growth of design complexity. Highlighting latest performance gains that made 3nm designs possible including simulations results.

User2User EU 2024 SESSION

LG - Accelerating Verification of PLLs for Wireless

Learn how Siemens SPICE and mixed-signal simulation tools helped LG achieve significant performance and productivity improvements for PLL IP verification versus previous solutions.