Avery Verification IP
Avery In-Circuit Simulation (ICS)
Accelerated confidence in co-development and co-verification of RTL hardware and firmware/software layers, associated with VIP Interface Protocols
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Why Avery VICS?
Extend verification IP upwards into firmware and software co-simulation - accelerated confidence by enabling co-development.
System-Level Co-Simulation includes:
- Complete System-level simulation of actual Linux host OS/SW and SoC HW RTL and embedded SW/FW
- Virtual platform co-simulation bridges virtual platform (host, embedded) and SoC RTL designs
- Support for QEMU and Arm Fast Models based virtual platform solutions
- Seamless transition from simulation VIP-based verification to full virtual platforms
- Leverage existing SV/UVM testbenches and VIPs for debugging capabilities
- Support for HW-SW co-debug, co-verification
Co-simulations
Avery's CXL virtual platform and VIP co-simulation helped reduce our validation time as we were able to perform extensive pre-silicon verification on our Leo Memory Connectivity Platform that supports CXL 2.0 and 1.1 technologies, and we are ready for real-world deployment. We look forward to utilizing a similar approach as we evolve next generation CXL designs.
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Get in touch with our sales team: 1-800-547-3000 or 1-503-685-8000
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Verification Academy
Verification Academy provides the skills necessary to mature an organization's functional verification process capabilities, providing a methodological bridge between high-level value propositions and the low-level details.
Verification Horizons blog
Insight and updates on concepts, values, standards, methodologies, and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them.
Verification Horizons
The Verification Horizons publication provides concepts, values, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them.