Avery Verification IP
Avery In-Circuit Simulation (ICS)
Accelerated confidence in co-development and co-verification of RTL hardware and firmware/software layers, associated with VIP Interface Protocols
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Why Avery VICS?
Extend verification IP upwards into firmware and software co-simulation - accelerated confidence by enabling co-development.
System-Level Co-Simulation includes:
- Complete System-level simulation of actual Linux host OS/SW and SoC HW RTL and embedded SW/FW
- Virtual platform co-simulation bridges virtual platform (host, embedded) and SoC RTL designs
- Support for QEMU and Arm Fast Models based virtual platform solutions
- Seamless transition from simulation VIP-based verification to full virtual platforms
- Leverage existing SV/UVM testbenches and VIPs for debugging capabilities
- Support for HW-SW co-debug, co-verification
Co-simulations
- Validate CXL 2.0 Type 3 SLD/MLD and Type 2 designs before actual Intel host servers with native CXL support available
- Avery customized QEMU virtual emulator runs standard Ubuntu/Linux kernels with CXL support (5.19)
- Reference testbench with CXL devices supporting multi-HDM, multi-channel DDR5 UDIMMs
- Supports CXLCV, diagnostics, and benchmarking applications
- Target CXL Root Port and CXL Device
- Supports single and multiple hosts including SVCS and MVCS switch environments
- Validate PCIe/NVMe peripherals
- P2P and Switch topologies
- Validate host processors IO subsystems
- Run UNH-IOL INTERACT NVMe SSD tests
- Run SPDK/FIO NVMe benchmarks
- Run PCIeCV compliance tool (Linux version)
- Validate USB hubs/devices including UAS/BOT storage
- P2P and Hub topologies
- Run USB Command Verifier tools from usb.org
- USB2CV (USB 2.0)
- USB3CV (USB 3.0)
- USB4CV (USB4)
- XHCICV (XHCI host)
- Generate real network traffic workloads
- Supports Native hosts (Host OS) and VMs (QEMU/Vmware – guest OS)
- Test SoC hardware offload implementations
- IPsec/MACsec, SSL, etc.
- Stress test DPU designs running multiple HW-SW protocols
- Offload storage, GPUs, memory to composable pooled arrays
- Host-to-DPU fabric is 100/200/400Gbe
- Debug custom SDKs and network interface drivers and end-user applications
- Run NVMe-oF SDKs and compliance and interoperability tests
- Run SPDK and FIO performance benchmarking applications
- UNH-IOL NVMe/TCP and NVMe/RoCE INTERACT tool and testsuite
Avery's CXL virtual platform and VIP co-simulation helped reduce our validation time as we were able to perform extensive pre-silicon verification on our Leo Memory Connectivity Platform that supports CXL 2.0 and 1.1 technologies, and we are ready for real-world deployment. We look forward to utilizing a similar approach as we evolve next generation CXL designs.
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Insight and updates on concepts, values, standards, methodologies, and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them.
Verification Horizons
The Verification Horizons publication provides concepts, values, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them.