Avery Verification IP for PCIe

With Avery Verification IP for PCIe, you get dynamically configurable BFMs supporting root complex, endpoint and switch. Compile once and select configuration at runtime as RC or EP. BFM randomly configures DUT during enumeration to test more supported configurations in less time such as randomizing equalization (coefficients, presets, reject coefficients) where many PHY layer issues are found.

Other features include:

• Root complex BFM mirrors DUT configuration enabling context-based validation
• Inject errors at all layers using callbacks and packet operations such as nullify, drop, nak, field override, etc.
• Transaction class and multi-function request/completion queues makes modeling large, high bandwidth, interleaved, delayed traffic request and completion streams easy. Stream TLPs based on random source request function and target memory and config space.
• SV constraint set on all packet and transaction classes generates rich set of normal and error packets
• Multi-level protocol trackers (TL, DLL, PL) makes debugging faster
• Functional coverage tracks TLP/DLLP commands and device states
• Comprehensive assertions track PCI-SIG compliance checklist coverage and isolate DUT bugs faster
• Comprehensive directed and constrained random compliance test suite achieves high protocol coverage