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Avery Verification IP

Avery Verification IP for Multimedia

Accelerated confidence in simulation-based verification of RTL designs with multimedia interfaces such as HDMI or DisplayPort

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Computer displays depicting video creation activity.

Why Avery Verification IP for Multimedia?

Get support for both Displayport and HDMI ecosystems, protocols and features with Avery Verification IP for Multimedia.

Avery Verification IP for HDMI

A comprehensive VIP solution for HDMI 2.0 source and sink designs. HDMI-Xactor implements a complete set of models, protocol checkers, and compliance testsuites in 100% native SystemVerilog and UVM.

Deliverables

  • HDMI BFM
  • Compliance testsuite
  • User guide

Features of Avery Verification IP for HDMI include:

  • Support of standards from HDMI.org and VESA
  • HDMI revision 2.0b, CEA-861-F, E_EDID_Standard, DSC 1.2, EDDC revision 1.0
  • CTS 2.0b/1.4b testsuite
  • Verification of both transmitter/source and receiver/sink and PHY designs
  • Automated dynamic Video and Audio traffic generation and PHY bit rate clock generation delivering fully accurate frame synchronization timing of multiple video and audio sources based on various shaping parameters including random receiver/sink device peripheral parameter set, interleaved/multiple packet control, interleaved frames control, line and frame blanking intervals
  • Standard DSC extensions
  • Comprehensive protocol checking and coverage reports
  • Protocol analyzer tracker report at all layers
  • Error injection and scoreboarding supported through Automated Frame Generation common callback for layer-specific

Protocol Family 

Standard Organization 

Sub Protocol 

Models 

HDMI 

HDMI 

HDMI 2.1 

HDMI CTS 2.1b Source/Sink 

HDMI CTS 2.1c Repeater 

Avery Verification IP for DisplayPort/eDP/DSC/DPI

A comprehensive VIP solution for DisplayPort (DP) and eDP source and sink designs. DP VIP implements a complete set of models, protocol checkers and compliance testsuites in 100% native SystemVerilog and UVM . Comprehensive support for DP/eDP source and sink design verification.

Deliverables

  • Source, Sink, Repeater BFMs
  • Compliance Testsuites
  • User guide

Avery Verification IP for DisplayPort/eDP/DSC/DPI includes:

  • Verification of transmitter/source, repeater and bridge and PHY designs
  • SST, MSO, and MST multi-stream transport
  • AUX channel services
  • Audio-Audio and Audio-Video synchronization
  • ALPM
  • Supports I2C over AUX CH and EDID
  • Supports DPCD registers
  • PHY features include 1-4 lanes, inter-lane skew, receiver de-skew
  • Adaptive Sync
  • Supports SSC
  • Supports packing of all video RGB, YCBCR444,
  • YCBCR422 and RAW color formats and frame rates
  • HPD based link training
  • Supports HDCP 1.4, 2.2, 2.3 SST and MST
  • Supports Display Stream Compression (DSC)
  • Supports Display Parallel Interface (DPI) for pixel stream interface
  • SPD and Main Stream Attribute (MSA) packets
  • Comprehensive protocol checking and coverage report
  • Functional traffic, error, and operational and power modes coverage
  • Protocol analyzer tracker report at all layers
  • Error injection and scoreboarding
  • Native SystemVerilog UVM
  • Standards-based and custom Avery Conformance testsuites
  • Verified with multiple IP vendor partners

Protocol Family 

Standard Organization 

Sub Protocol 

Models 

DP 

VESA 

DP 2.0.1 

PICSIG 

PIPE 4.2 

VESA 

VESA DisplayPort v1.4a Link Layer Compliance Test Specification(Link CTS) Revision 1.0 

VESA 

VESA DisplayPort v1.4a PHY Layer Compliance Test Specification (PHY CTS) Revision 1. 

eDP 

VESA 

eDP 1.4b 

VESA 

VESA eDP Link Layer Compliance Test Guide v1.0 

VESA 

VESA eDP Source PHY Compliance Test Guide v1.0 

VESA 

HDCP 1.4/1.3, HDCP 2.3/2.2 

CEA 

CEA-861-F 

DSC 

VESA 

DSC 1.2 

DPI 

MIPI 

DPI-2 

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