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Avery Verification IP

Avery Verification IP for Mobile Protocols

Accelerated confidence in simulation-based verification of RTL designs with mobile protocol interfaces such as Soundwire, MIPI CSI, DSI, C_PHY, D_PHY

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Why Avery Verification IP for Mobile protocols?

Avery VIP for Mobile protocols is a complete solution to verify Mobile (Unipro, M-Phy, Soundwire, CSI, DSI, C-PHY, D-PHY) based IP and SoC products that use those protocols.

Avery Verification IP for Soundwire

A comprehensive VIP solution portfolio for Soundwire 1.0 used by SoC and IP designers to ensure comprehensive verification and protocol and timing compliance. Soundwire-Xactor implements a complete set of models, protocol checkers, and compliance testsuites in 100% native SystemVerilog and UVM.

Deliverables

  • Soundwire BFM
  • Compliance testsuite
  • User guide

Avery Verification IP for Soundwire features include:

  • Complete set of models for Soundwire master, monitor and device verification
  • Master model can configure multiple data ports, frame shapes dynamically, and generate payload streams to verify master and slave designs in complex system topologies
  • System-level operations supported including allocating master and slave devices class objects (BFMs) to slave device map table and determines frame size and shape, sample interval and stream synchronization point including randomly configuration
  • Automated payload streams generation per port based on stream class parameters such as Data lane(s) used by each data payload stream, source/sink(s) of each data payload streams, # of channels, Sample size and rate, and frame positioning parameters
  • Multiple isochronous and asynchronous audio payload streams including PDM, PCM and random data
  • Inject errors at all layers through callbacks
  • Comprehensive assertions track Soundwire compliance coverage
  • Functional coverage tracks range commands, payload transport modes, frame shapes, payload transport status
  • Bus Protocol Analyzer depicts frame commands, payload/channel streams for each device, and frame and sub-frame map
  • Comprehensive directed and constrained random compliance testsuite for Soundwire slave device achieves high protocol coverage
  • Functional coverage tracks range of packet traffic, FSMs and complex operational sequences
  • Tracker log monitors all levels and improves debug

Protocol Family 

Standard Organization 

Sub Protocol 

Models 

Soundwire 

MIPI 

SoundWire 1.0 

Avery Verification IP for CSI/DSI/C-PHY/D-PHY

A comprehensive VIP solution for CSI-2, DSI-2, D-PHY and C-PHY transmitter and receiver designs. CSI/DSI-Xactor implements a complete set of models, protocol checkers and compliance testsuites in 100% native SystemVerilog and UVM.

Deliverables

  • CSI-2 BFM
  • DSI-2 BFM
  • C-PHY BFM
  • D-PHY BFM
  • Compliance testsuite
  • User guide

Avery Verification IP for CSI/DSI/C-PHY/D-PHY features include:

  • Verification of both transmitter/source and receiver/sink and PHY designs DSI-2 with C-PHY and D-PHY, CSI-2 with C-PHY and D-PHY
  • Automated dynamic Video and Audio traffic generation and PHY bit rate clock generation delivering fully accurate frame synchronization timing of multiple video and audio sources based on various shaping parameters including random receiver/sink device peripheral parameter set, interleaved/multiple packet control, interleaved frames control, line and frame blanking intervals
  • Standard DSC extensions
  • Comprehensive protocol checking and coverage report
  • Functional traffic, error, and operational and power modes coverage
  • Standard DSC extensions
  • Comprehensive protocol checking and coverage reports
  • Protocol analyzer tracker report at all layers
  • Error injection and scoreboarding supported through Automated Frame Generation common callback for layer-specific
  • Inspection and error injection using methods to in-line
  • Modify, drop, inject packet ahead/behind, force next state
  • Standards-based and custom Avery Conformance testsuites
  • Verified with multiple IP vendor partner
  • Perform receiver configuration
  • Execute sleep modes including SLM sequence
  • Perform receiver error detection
  • DSI-2 DSC 1.1 supported
  • CSI-2 data compression for RAW Data types supported
  • CSI TX/RX and C-PHY/D-PHY Conformance tests
  • D-PHY and C-PHY model support TX and RX HS, LP, and FEN, CNN
  • System power-up and initialization
  • Bidirectional signalling control mode and video mode systems
  • Read, ACK, Error reporting
  • Forward escape ULPS for sleep modes
  • Multi-lane distribution and merging
  • Multi-lane interoperability (TX X-lanes, RX Y-lanes)
  • D-PHY specific deskew calibration including bypass and periodic
  • C-PHY specific enable/Disable 3-phase encoding

Protocol Family 

Standard Organization 

Sub Protocol 

Models 

CSI 

MIPI 

CSI-2 v4.0 

CSI-2 TX/RX CTS v3 

DSI 

MIPI 

DSI-2 v2.0 

DSI-2 CTS v1.1 

C-PHY 

MIPI 

C-PHY v2.1 

C-PHY v2.0 CTS 1.0 

D-PHY 

MIPI 

D-PHY v3.0 

D-PHY v2.1 CTS v1.1 

A-PHY 

MIPI 

A-PHY v1.0 

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Verification Academy provides the skills necessary to mature an organization's functional verification process capabilities, providing a methodological bridge between high-level value propositions and the low-level details.

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Verification Horizons blog

Insight and updates on concepts, values, standards, methodologies, and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them.

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Verification Horizons

The Verification Horizons publication provides concepts, values, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them.

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