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Avery Verification IP

Avery Verification IP for Embedded Storage

Accelerated confidence in simulation-based verification of RTL designs with embedded storage interfaces such as UFS, UniPro, M-PHY

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A set of UFS format miniature memory storage cards.

Why Avery Verification IP for Embedded Storage?

Verify Embedded Storage (UFS, eMMC, SD, UHS) based IP and SoC products that use Embedded Storage interfaces.

UFS / UniPro / M-PHY VIP

A comprehensive VIP solution portfolio for UFS Host Controller (UFSHCI), UFS, and UME including MIPI UniPro and M-PHY used by SoC and IP designers to ensure comprehensive verification and protocol and timing compliance to the JEDEC standards. UFS VIP implements a complete set models, protocol checkers, and compliance test suites in 100% native SystemVerilog and UVM.

Deliverables

  • UFSHC host driver BFM
  • Generic UFS host driver BFM
  • UFS device BFM
  • UniPro BFM
  • M-PHY BFM
  • Compliance testsuite
  • User guide

UFS host supported 2 ways:

  • UFSHC 4.0 Driver model supports UME 1.0 and implements UFSHCI programming interface including host adapter to various host bus interfaces including AMBA AXI and AHB
  • Generic Host model emulates UFSHC host driver and UFSHCI-based controller
  • UFS 4.0 Device model emulates simple UFS device including sparse logical block storage and processes over 20 SCSI
  • Supports command sets: Native UFS and SCSI SPC-4, SBC-3, and SAM-5
  • Supports UFS DME and CPort Users
  • CPort adaptor interfaces to Avery or 3rd party UniPro IP/VIP enabling mix and match between UFS and Unipro layers support module-level integration and verification
  • M-PHY Model
  • Support draft M-PHY 5.0
  • Multiple LANE provisions
  • Multiple transmission modes include LS-MODE NRZ and PWM signalling
  • Multiple power saving modes
  • Support Error Injections (encoding, disparity etc)
  • UniPro Model
  • Emulates UniPro 2.0 protocol stack layers and M-PHY
  • Supports all service primitives (SAP) and service data units (x_SDU)
  • DME User supports all sequences of control, configuration, and status primitives
  • Transport service
  • Allocates connections between CPorts
  • Schedules message transfers between CPort Users
  • Supports CPort signal interface
  • Supports UniPro Test Feature
  • Inject errors at all layers through callbacks
  • Comprehensive assertions track UFS and MIPI compliance coverage
  • Functional coverage tracks range of packet traffic, FSMs, and complex operational sequences
  • Tracker log monitors all levels and improves debug
  • Comprehensive directed and constrained random compliance testsuite for UFSHCI and UFS device achieves high protocol coverage

Protocol Family 

Standard Organization 

Sub Protocol 

Models 

UFS 

JEDEC 

UFS 3.1 

JESD220E 

JEDEC 

UFS 4.0 

UFS 4.0 TG Concensus Ballots 

HPB 2.0 

JESD220-3A 

JEDEC 

UFS HCI 3.0 

JESD223D 

UFS HCI 4.0 

UFS 4.0 TG Concensus Ballots 

Unipro 

MIPI 

UniPro 2.0 R07 

Unipro 1.8 CTS 1.0 

M-PHY 

MIPI 

M-PHY 5.0 

eMMC VIP

A comprehensive VIP solution portfolio for SDIO 4.0 and UHS-II used by SoC and IP designers to ensure comprehensive verification and protocol and timing compliance. SD-Xactor implements a complete set of models, protocol checkers and compliance testsuites in 100% native SystemVerilog and UVM.

Deliverables

  • SD host BFM
  • Compliance testsuite
  • User guide
  • Perform bring-up of I/O Aware and Non-I/O Aware, Non-UHS-II and UHS-II, and Combo devices and supports bus modes and speeds including SPI, 1-bit & 4-bit SD Data (HS, LS), and UHS-II (FD: 2D1U-FD, 1D2U-FD, 2D2U-FD and 2L-HD)
  • Supports all commands including erase, trim, sanitize, discard, and write protect commands, power modes including legacy power down (SD memory) and suspend/resume (SDIO Card), and UHS-II Hibernate, and suppots SDIO interrupt modes
  • Host and Device models can be used in active and monitor only modes and supports bypass mode to skip power-on reset
  • Open and unencrypted timing class models all timing parameters (randomize, modifiable)
  • SV constraint set on all transaction classes generates rich set of normal and error packets
  • Host randomly configures SD DUT including card registers, function extension registers, CIA
  • Inject errors at all layers through callbacks
  • Comprehensive protocol and timing checks track compliance checklist coverage and isolate DUT bugs faster
  • Tracker log monitors all levels and improves debug
  • Comprehensive directed and constrained random compliance testsuite achieves high protocol coverage

Protocol Family 

Standard Organization 

Sub Protocol 

Models 

eMMC 

JEDEC 

eMMC 5.2 

JESD84-B52 

SD 4.0 + UHS-II VIP

A comprehensive VIP solution portfolio for SDIO 4.0 and UHS-II used by SoC and IP designers to ensure comprehensive verification and protocol and timing compliance. SD-Xactor implements a complete set of models, protocol checkers, and compliance testsuites in 100% native SystemVerilog and UVM.

Deliverables

  • SD host BFM
  • Compliance testsuite
  • User guide
  • Perform bring-up of I/O Aware and Non-I/O Aware, Non-UHS-II and UHS-II, and Combo devices and supports bus modes and speeds including SPI, 1-bit & 4-bit SD Data (HS, LS), and UHS-II (FD: 2D1U-FD, 1D2U-FD, 2D2U-FD and 2L-HD)
  • Supports all commands including erase, trim, sanitize, discard, and write protect commands, power modes including legacy power down (SD memory) and suspend/resume (SDIO Card), and UHS-II Hibernate, and suppots SDIO interrupt modes
  • Host and Device models can be used in active and monitor only modes and supports bypass mode to skip power-on reset
  • Open and unencrypted timing class models all timing parameters (randomize, modifiable)
  • SV constraint set on all transaction classes generates rich set of normal and error packets
  • Host randomly configures SD DUT including card registers, function extension registers, CIA
  • Inject errors at all layers through callbacks
  • Comprehensive protocol and timing checks track compliance checklist coverage and isolate DUT bugs faster
  • Tracker log monitors all levels and improves debug
  • Comprehensive directed and constrained random compliance testsuite achieves high protocol coverage

Protocol Family 

Standard Organization 

Sub Protocol 

Models 

SD 

SDCARD 

SDIO Ver9.0 

SDCARD 

UHS-II Ver1.02 

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