Accelerated confidence in simulation-based verification of RTL designs with control/serial bus interfaces such as I2C, SPI, UART, JTAG
A comprehensive memory VIP solution portfolio for I3C and I2C s used by system-on-chip (SoC) and IP designers to ensure comprehensive verification and protocol and timing compliance. Avery Verification IP for Control/Serial Buses implements a complete set of models, protocol checkers and compliance testsuite in 100% native SystemVerilog and UVM.
Deliverables
Avery Verification IP for Control/Serial Buses features include:
Protocol Family | Standard Organization | Sub Protocol | Models |
|---|---|---|---|
SMBUS | System Management Interface Forum | SMBUS Ver 3.1 | |
I2C | NXP | UM10204 | |
I3C | MIPI | I3C 1.1 | |
MIPI | I3C HCI 1.1 | ||
MIPI | I3C Basic 1.1 | ||
MIPI | I3C Debug 1.0 | ||
MIPI | SPP 2.0 | ||
MIPI | STP 2.2 |
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