Accelerated confidence in simulation-based verification of RTL designs with ARM AMBA bus interfaces such as AXI, AHB, APB, CHI, ACE
Enable system-on-chip (SoC) and IP developers to perform comprehensive functional verification of their IP and SOCs. Avery Verification IP for AMBA incorporates the full range of AMBA bus protocols (AXI4 – Full, Lite, Stream, AXI3, AHB, APB, CHI) master, slave and interconnects functionalities and ensure compliance to the AMBA standards.
Deliverables
Support master, slave, and Interconnect BFMs including passive interconnect monitor. The transaction class supports SV constraint sets for interleaving, out of order, early write data phase, inter-transaction and inter-beat delays, size/length, addressing. Other features include:
Protocol Family | Standard Organization | Sub Protocol | Models |
|---|---|---|---|
AXI | Arm | AXI5 | |
AHB | Arm | AHB5 | |
APB | Arm | APB3 | |
ACE | Arm | ACE5 | |
CHI | Arm | CHI E.a |
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