Avery Verification IP for AMBA

Support master, slave, and Interconnect BFMs including passive interconnect monitor. The transaction class supports SV constraint sets for interleaving, out of order, early write data phase, inter-transaction and inter-beat delays, size/length, addressing. Other features include:

• ACE interconnect monitor verifies cache state transitions ACE supports N-way and fully associative cache
• Inject errors at all layers using callbacks and control slave completion response
• SV constraint set for transaction classes generates rich set of normal and error requests and responses
• Multi-level protocol trackers (Cache state, Channel) makes debugging faster
• Functional coverage tracks commands, addresses, and attributes
• Interfaces to ARM protocol checkers to isolate DUT bugs faster
• Comprehensive directed and constrained random examples of all transfer types