Questa Advanced Simulator

Overview

Questa Advanced Simulator

The Questa Advanced Simulator is the core simulation and debug engine of the Questa Verification Solution; the comprehensive advanced verification platform capable of reducing the risk of validating complex FPGA and SoC designs.


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Questa Simulation tools enable design teams to verify the architecture and behavior planned for an implementation.
Key Features

Advanced Verilog Simulator

The Questa Advanced Simulator achieves industry-leading performance and capacity through very aggressive, global compile and simulation optimization algorithms for SystemVerilog and VHDL.

Industry-leading

High Performance and Capacity

Using its advanced algorithms, the Questa Advanced Simulator can help you improve SystemVerilog and mixed VHDL/SystemVerilog RTL simulation performance by up to 10X.

The Questa Advanced Simulator is the core simulation and debug engine of the Questa Verification Solution; the comprehensive advanced verification platform capable of reducing the risk of validating complex FPGA and SoC designs.
Multi-core simulation

High-performance, multi-language engine

The Questa Advanced simulator supports all design languages and constructs, and either automatically or manually partitions the design to run in parallel while maintaining a single database for debug and coverage.

Questa Simulation tools enable design teams to verify the architecture and behavior planned for an implementation.
Automated stimuli generation

Testbench Automation

The Questa Advanced Simulator supports the most comprehensive solutions for testbench automation in the industry, enabling automatic creation of complex, input-stimuli using SystemVerilog or SystemC Verification (SCV) library constructs, and combining these forms of stimulus generation with functional coverage to identify the functionality exercised by the automatically-generated stimulus.

The Questa Advanced Simulator supports the most comprehensive solutions for testbench automation in the industry, enabling automatic creation of complex, input-stimuli using SystemVerilog or SystemC Verification (SCV) library constructs, and combining these forms of stimulus generation with functional coverage to identify the functionality exercised by the automatically-generated stimulus.
Questa Simulation & Verfication

White Papers

Questa Simulation & Verfication

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Verification Academy

Verification Academy provides the skills necessary to mature an organization's functional verification process capabilities, providing a methodological bridge between high-level value propositions and the low-level details.

Verification Horizons Blog

Insight and updates on concepts, values, standards, methodologies, and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them.

Verification Horizons Issue

The Verification Horizons publication provides concepts, values, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them.