Questa Verification & Simulation

Combines high performance, high capacity simulation with unified debug and functional coverage for complete native support of Verilog, SystemVerilog, VHDL, SystemC, SVA, UPF and UVM.

The industry’s most advanced portable stimulus testbench automation solution, achieving coverage goals 10 to 100X faster than constrained random testing and scaling across all design levels.

Power-aware simulation automatically verifies architecture and behavior of active power management structures in RTL and gates early in design flows to achieve optimal power reduction at least cost.

A shared platform and environment for comprehensive verification management of design process, tools and data within a scalable, modular solution.

Simplifies, automates and enables requirements traceability from specification of hardware through HDL coding, implementation and validation.