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Overview

Questa RDC Verification

Questa RDC leverages the CDC path and waiver information taken from Questa CDC analysis, then executes a comprehensive, formal-based analysis that focuses on the actual functional reset-domain crossing paths for high throughput and the most deterministic path to actionable results.

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Questa RDC leverages the CDC path and waiver information taken from Questa CDC analysis, then executes a comprehensive, formal-based analysis that focuses on the actual functional reset-domain crossing paths for high throughput and the most deterministic path to actionable results.
KEY FEATURES

Questa RDC Verification

Reset-domain crossings (RDCs) can expose a design to data loss or control signal corruption, just like clock-domain crossings. Questa RDC formally and exhaustively verifies reset-domain crossings, providing a high-value, low-effort path to extending your domain crossing verification to RDCs.

HIGH PERFORMANCE

Sophisticated, Exhaustive Analysis

Questa RDC is designed to automatically employ formal analysis to exhaustively identify RDC issues in your design. Specifically, taking your RTL as input, Questa RDC automatically performs an exhaustive, bottom-up reset tree analysis, then automatically generates and proves assertions that cover numerous reset-domain specific structural checks.

Questa RDC is designed to automatically employ formal analysis to exhaustively identify RDC issues in your design. Specifically, taking your RTL as input, Questa RDC automatically performs an exhaustive, bottom-up reset tree analysis, then automatically generates and proves assertions that cover numerous reset-domain specific structural checks.
EASY SET-UP

Rapid Bring-Up

Direct reuse of Questa CDC RTL-level setups, constraints, waivers, and results enables reset-domain and clock groupings to be automatically inferred and reported. Automated incorporation of synthesis design constraints (SDC), Liberty models, and Unified Power Format (UPF) specifications further expedites bring-up.

Direct reuse of Questa CDC RTL-level setups, constraints, waivers, and results enables reset-domain and clock groupings to be automatically inferred and reported. Automated incorporation of synthesis design constraints (SDC), Liberty models, and Unified Power Format (UPF) specifications further expedites bring-up.
SUPPORT FOR EXPERTS & NOVICES

Ease of Use

Reset signaling and clock groupings are automatically inferred and reported with each run to confirm there are no unexpected changes. Questa RDC pinpoints all potential RDC issues and automatically identifies any existing RDC synchronization structures. No testbench is required. Custom synchronizers can be created for proprietary synchronization strategies.

Reset signaling and clock groupings are automatically inferred and reported with each run to confirm there are no unexpected changes. Questa RDC pinpoints all potential RDC issues and automatically identifies any existing RDC synchronization structures. No testbench is required. Custom synchronizers can be created for proprietary synchronization strategies.
Questa Design Solutions

Questa RDC Verification Resources

The increase in reset signaling complexity, along with the emergence of multiple reset signaling networks in devices, is creating new verification challenges that cannot be addressed by RTL simulation. Questa RDC uses formal analysis methods to identify reset-domain crossing issues.

On-Demand webinar | Improving initial RTL quality
Improve RTL quality-focused flow
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Improving initial RTL quality

ON-DEMAND WEBINAR

This session will help you lower risks and improve team agility and development consistency by optimizing verification. Using designer-driven verification flows, designers get intent-focused insight to find issues to fix.

Questa CDC finds errors using structural analysis to detect clock-domains, synchronizers, and low power structures via the UPF. It then generates assertions and metastability models for protocol and reconvergence verification.
CDC VERIFICATION
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Questa Clock-Domain Crossing (CDC) Verification

Questa CDC finds errors using structural analysis to detect clock-domains, synchronizers, and low power structures via the UPF. It then generates assertions and metastability models for protocol and reconvergence verification.

Questa Signoff CDC builds on Questa CDC RTL analysis and automatically generates and analyzes assertions to rapidly identify chip-killing glitches and other clock-domain crossing issues.
SIGNOFF CDC
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Questa Signoff CDC

Questa Signoff CDC builds on Questa CDC RTL analysis and automatically generates and analyzes assertions to rapidly identify chip-killing glitches and other clock-domain crossing issues.

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Verification Academy

Verification Academy provides the skills necessary to mature an organization's functional verification process capabilities, providing a methodological bridge between high-level value propositions and the low-level details.

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Verification Horizons Blog

Insight and updates on concepts, values, standards, methodologies, and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them.

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Verification Horizons Issue

The Verification Horizons publication provides concepts, values, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them.

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