Questa CDC identifies errors using structural analysis to recognize clock-domains, synchronizers, and low power structures via the Unified Power Format (UPF). It generates assertions for protocol verification along with metastability models for reconvergence verification.
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Using only your RTL (and UPF power intent file), Questa CDC solutions automatically generate and analyze assertions to rapidly identify chip-killing clock-domain crossing (CDC) issues.
TARGETING CDC CHALLENGES
Using only your RTL and UPF power intent file, Questa CDC solutions automatically generate and analyze assertions to rapidly identify chip-killing clock-domain crossing (CDC) issues.
CAPACITY AND EFFICIENCY
When analyzing billion-gate designs, minimizing “noise” is critical. Questa CDC comprehensive, hierarchical, formal-based analysis searches through DUT elements for high throughput and noise minimization, simultaneously providing industry-leading scalability and high quality of results, while enabling CDC IP reuse.
Questa CDC supports the Synthesis Design Constraints (SDC) format for clock- and port- domain settings, and it includes a TCL scripting environment with powerful control and reporting capabilities. Questa CDC automatically identifies your clocks and clock distribution strategy minimizing set-up time.
Questa CDC automatically identifies errors related to clock-domain crossings—signals/groups of signals generated in one clock-domain and consumed in another. The technology checks all potential failure modes and presents the user with familiar schematic and waveform displays.
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Verification Academy provides the skills necessary to mature an organization's functional verification process capabilities, providing a methodological bridge between high-level value propositions and the low-level details.
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