Questa Signoff CDC

Overview

Questa Signoff CDC Analysis

Questa Signoff CDC automatically identifies the clock and clock distribution strategy, minimizing set up time. Simply read in your gate-level design as well as the RTL-level results from Questa CDC, and Questa Signoff CDC will pinpoint all potential gate-level CDC issues – no testbench is required.


Get in touch with our sales team: 1-800-547-3000

Questa Signoff CDC automatically identifies the clock and clock distribution strategy, minimizing set up time. Simply read in your gate-level design as well as the RTL-level results from Questa CDC, and Questa Signoff CDC will pinpoint all potential gate-level CDC issues – no testbench is required.
Key Features

Questa Signoff CDC

Questa Signoff CDC identifies errors associated with clock domain crossing issues created by the implementation process – either disruption of synchronizer circuitry required to eliminate CDC-induced metastability issues, or signal glitches introduced into the synthesized logic.

Low noise, high accuracy

Exacting Results

Fewest false alarms in the industry, so you don’t waste time chasing non-issues, and instead can quickly root cause and resolve actual design flaws. Tight integration with the Questa CDC RTL verification app, reusing all the CDC path and waiver information created at the RTL level to expedite the gate-level analysis and significantly reduce “noise” from false negatives



Questa CDC finds errors using structural analysis to detect clock-domains, synchronizers, and low power structures via the UPF. Questa RDC formally verifies reset domain crossings to exhaustively identify reset domain crossing issues in SoC and system designs. Questa Signoff CDC automatically generates and analyzes assertions to rapidly identify chip-killing glitches and other clock domain crossing  issues.

High performance

SoC-level Scalability

Questa Signoff CDC high performance analysis can process over 100-million-gate designs, and its hierarchical capabilities enable unlimited capacity.

Questa CDC finds errors using structural analysis to detect clock-domains, synchronizers, and low power structures via the UPF. Questa RDC formally verifies reset domain crossings to exhaustively identify reset domain crossing issues in SoC and system designs. Questa Signoff CDC automatically generates and analyzes assertions to rapidly identify chip-killing glitches and other clock domain crossing  issues.

Immediate Productivity

Ease of use

Automatically infers clock grouping, re-groups logic belonging to CDC synchronization structures, and re-groups any “bit blasted” busses to prevent redundant violation reports. Supports advanced hierarchical methods to maximize turn-around time. Direct re-use of Questa CDC RTL-level setup information, constraints, waivers and results. Automated SDC import and debug and Liberty models are also supported.

Questa CDC finds errors using structural analysis to detect clock-domains, synchronizers, and low power structures via the UPF. Questa RDC formally verifies reset domain crossings to exhaustively identify reset domain crossing issues in SoC and system designs. Questa Signoff CDC automatically generates and analyzes assertions to rapidly identify chip-killing glitches and other clock domain crossing  issues.

Questa Signoff CDC Resources

Questa Signoff CDC runs deep formal analysis on automatically generated assertions, integrating structural, functional and formal algorithms to verify gate-level CDC structures and automatically identifying glitches that might be introduced during the synthesis and implementation process.

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