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Overview

Questa RDC Verification

Questa RDC leverages the CDC path and waiver information taken from Questa CDC analysis, then executes a comprehensive, formal-based analysis that focuses on the actual functional reset-domain crossing paths for high throughput and the most deterministic path to actionable results.


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Questa Factsheets provide detailed product descriptions and specifications.

Questa RDC Resources

The increase in reset signaling complexity, along with the emergence of multiple reset signaling networks in devices, is creating new verification challenges that cannot be addressed by RTL simulation. Questa RDC uses formal analysis methods to identify reset-domain crossing issues.

Key Features

Questa RDC Verification

Reset-domain crossings (RDCs) can expose a design to data loss or control signal corruption, just like clock-domain crossings. Questa RDC formally and exhaustively verifies reset-domain crossings, providing a high-value, low-effort path to extending your domain crossing verification to RCDs.

High performance

Sophisticated, Exhaustive Analysis

Questa RDC is designed to automatically employ formal analysis to exhaustively identify RDC issues in your design. Specifically, taking your RTL as input, Questa RDC automatically performs an exhaustive, bottom-up reset tree analysis, then automatically generates and proves assertions that cover numerous reset-domain specific structural checks.

Questa CDC finds errors using structural analysis to detect clock-domains, synchronizers, and low power structures via the UPF. Questa RDC formally verifies reset domain crossings to exhaustively identify reset domain crossing issues in SoC and system designs. Questa Signoff CDC automatically generates and analyzes assertions to rapidly identify chip-killing glitches and other clock domain crossing  issues.

Easy set-up

Rapid Bring-Up

Direct reuse of Questa CDC RTL-level setups, constraints, waivers, and results enables reset-domain and clock groupings to be automatically inferred and reported. Automated incorporation of synthesis design constraints (SDC), Liberty models, and Unified Power Format (UPF) specifications further expedites bring-up.

Questa CDC finds errors using structural analysis to detect clock-domains, synchronizers, and low power structures via the UPF. Questa RDC formally verifies reset domain crossings to exhaustively identify reset domain crossing issues in SoC and system designs. Questa Signoff CDC automatically generates and analyzes assertions to rapidly identify chip-killing glitches and other clock domain crossing  issues.

Support for experts & novices

Ease of Use

Reset signaling and clock groupings are automatically inferred and reported with each run to confirm there are no unexpected changes. Questa RDC pinpoints all potential RDC issues and automatically identifies any existing RDC synchronization structures. No testbench is required. Custom synchronizers can be created for proprietary synchronization strategies.

Questa CDC finds errors using structural analysis to detect clock-domains, synchronizers, and low power structures via the UPF. Questa RDC formally verifies reset domain crossings to exhaustively identify reset domain crossing issues in SoC and system designs. Questa Signoff CDC automatically generates and analyzes assertions to rapidly identify chip-killing glitches and other clock domain crossing  issues.

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