Questa CDC identifies errors using structural analysis to recognize clock-domains, synchronizers, and low power structures via the Unified Power Format (UPF). It generates assertions for protocol verification along with metastability models for reconvergence verification.
Get in touch with our sales team: 1-800-547-3000
Using only your RTL (and UPF power intent file), Questa CDC solutions automatically generate and analyze assertions to rapidly identify chip-killing clock-domain crossing (CDC) issues.
Targeting CDC challenges
Using only your RTL and UPF power intent file, Questa CDC solutions automatically generate and analyze assertions to rapidly identify chip-killing clock-domain crossing (CDC) issues.
Capacity and efficiency
When analyzing billion-gate designs, minimizing “noise” is critical. Questa CDC comprehensive, hierarchical, formal-based analysis searches through DUT elements for high throughput and noise minimization, simultaneously providing industry-leading scalability and high quality of results, while enabling CDC IP reuse.
Immediate productivity
Questa CDC supports the Synthesis Design Constraints (SDC) format for clock- and port- domain settings, and it includes a TCL scripting environment with powerful control and reporting capabilities. Questa CDC automatically identifies your clocks and clock distribution strategy, minimizing set-up time.
Insight and updates on concepts, values, standards, methodologies, and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them.
The Siemens Support Center provides you with everything in one easy-to-use location – knowledgebase, product updates, documentation, support cases, license/order information, and more.
Access on-demand training, find online instructor-led training, attend instructor-led training in our training centers located in major cities worldwide, or schedule customized training tailored to the needs of your company.