Extending the Questa verification platform to include verification of circuits that contain analog IP, the Questa ADMS tool combines several high-performance simulation engines in one efficient tool, and supports every major hardware description language and exchange standard.
Event-driven verification models that are simulated directly in a high-speed for the fastest possible simulation
Continuous time AMS verification models for analog applications where high accuracy is necessary
Co-simulation between the digital RTL description and the analog SPICE design
SystemVerilog and UVM with mixed-signal extensions
Effective functional verification in presence of analog signals
Fast event-driven and real number verification modeling
Accurate AMS verification modeling
SVA applied to analog signals
Familiar Questa debugging environment
Analog testbenches applied to mixed-signal designs
Effective corner analysis in presence of digital signals
Familiar EZwave waveform display
Visual debugging of current contributions
Verification Academy provides the skills necessary to mature an organization's functional verification process capabilities, providing a methodological bridge between high-level value propositions and the low-level details.
Insight and updates on concepts, values, standards, methodologies, and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them.
The Verification Horizons publication provides concepts, values, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them.